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ADV7173KSTZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
REV. B
ADV7172/ADV7173
–37–
TELETEXT REQUEST CONTROL REGISTER TC07
(TC07–TC00)
(Address (SR4–SR0) = 1CH)
Teletext Control Register is an 8-bit-wide register. See Figure 59.
TTXREQ Rising Edge Control (TC07–TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles.
TTXREQ Falling Edge Control (TC03–TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for Teletext
data. Increasing this value reduces the amount of Teletext Bits
below the default of 360. If Bits TC03–TC00 are 00Hex when
Bits TC07–TC04 are changed, then the falling edge of TTXREQ
will track that of the rising edge (i.e., the time between the fall-
ing and rising edge remains constant).
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(Address (SR4–SR0) = 19H)
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 60
shows the operations under control of this register.
C/W BIT DESCRIPTION
CGMS Data (C/W03–C/W00)
These four data bits are the final four bits of CGMS data out-
put stream. Note it is CGMS data ONLY in these bit positions
i.e., WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (“1”), the last six bits of the CGMS
data, i.e., the CRC check sequence, are calculated internally by
the ADV7172/ADV7173. If this bit is disabled (“0”), the CRC
values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (“1”), CGMS is enabled for odd fields.
Note that this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (“1”), CGMS is enabled for even fields.
Note that this is only valid in NTSC mode.
Wide Screen Signal Control (C/W07)
When this bit is set (“1”), wide screen signalling is enabled.
Note that this is only valid in PAL mode.
TC01 TC00
TC07
TC02TC04 TC03TC05TC06
TTXREQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
0 0 0 0 0 PCLK
0 0 0 1 1 PCLK
" " " " " PCLK
1 1 1 0 14 PCLK
1 1 1 1 15 PCLK
TTXREQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0 0 0 0 0 PCLK
0 0 0 1 1 PCLK
" " " " " PCLK
1 1 1 0 14 PCLK
1 1 1 1 15 PCLK
Figure 59. Teletext Request Control Register
CGMS CRC CHECK
CONTROL
0 DISABLE
1 ENABLE
C/W04
WIDE SCREEN SIGNAL
CONTROL
0 DISABLE
1 ENABLE
C/W07
C/W07 C/W06 C/W05 C/W04 C/W03 C/W02 C/W01 C/W00
CGMS ODD FIELD
CONTROL
0 DISABLE
1 ENABLE
C/W05
C/W03–C/W00
CGMS DATA
CGMS EVEN FIELD
CONTROL
0 DISABLE
1 ENABLE
C/W06
Figure 60. CGMS_WSS Register 0
REV. B
ADV7172/ADV7173
–38–
CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10)
(Address (SR4–SR0) = 1AH)
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 61 shows
the operations under control of this register.
C/W1 BIT DESCRIPTION
CGMS/WSS Data (C/W15–C/W10)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these
bits are WSS data.
CGMS Data Only (C/W17–C/W16)
These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 C/W1(C/W27–C/W20)
(Address (SR4-SR0) = 1BH)
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 62
shows the operations under control of this register.
C/S BIT DESCRIPTION
CGMS/WSS Data (C/W27–C/W20)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these
bits are WSS data.
CONTRAST CONTROL REGISTER (CC07–CC00)
(Address (SR4–SR0) = 1DH)
The contrast control register is an 8-bit-wide register used to
scale the Y output levels. Figure 63 shows the operations under
control of this register.
CC0 BIT DESCRIPTION
Reserved (CC07–CC06)
A Logic “0” must be written to these bits.
Y Scalar Value (CC05–CC00)
These six bits represent the value required to scale the Y pixel
data from 0.75 to 1.25 of its initial level. The value of these six
bits is calculated using the following equation:
Contrast Control Register = (X –0.785) × 128
where X = Scaling factor for Y
e.g., Scale Y by 0.9
Contrast Control Register = (0.9–0.75) × 128 = 19.2 = 010011
(rounded to the nearest integer)
Actual scaling factor = 0.898.
C/W17 C/W16 C/W15 C/W14 C/W13 C/W12 C/W11 C/W10
C/W15–C/W10
CGMS/WSS DATA
C/W17–C/W16
CGMS DATA
Figure 61. CGMS_WSS Register 1
C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20
C/W27–C/W20
CGMS/WSS DATA
Figure 62. CGMS_WSS Register 2
CC07 CC06 CC05 CC04 CC03 CC02 CC01 CC00
CC05–CC00
Y SCALAR VALUE
CC07–CC06
ZERO SHOULD
BE WRITTEN
TO THESE BITS
Figure 63. Contrast Control Register
REV. B
ADV7172/ADV7173
–39–
COLOR CONTROL REGISTERS 2–1 (CC2–CC1)
(Address (SR4–SR0) = 1EH–1FH)
The color control registers are 8-bit-wide registers used to scale
the U and V output levels. Figure 64 shows the operations
under control of these registers.
CC1 BIT DESCRIPTION
Reserved (CC17–CC16)
A Logic “0” must be written to these bits.
U Scalar Value (CC15–CC10)
These six bits represent the value required to scale the U level
from 0.75 to 1.25 of its initial level. The value of these six bits is
calculated using the following equation:
Color Control Register 1 = (X – 0.75) × 128
where X = Scaling factor for U
e.g., Scale U by 0.8
Color Control Register 1 = (0.8 – 0.75) × 128 = 6.4 = 000110
(rounded to the nearest integer)
CC2 BIT DESCRIPTION
Reserved (CC27–CC26)
A Logic “0” must be written to these bits.
V Scalar Value (CC25–CC20)
These six bits represent the value required to scale the V pixel
data from 0.75 to 1.25 of its initial level. The value of these six
bits is calculated using the following equation:
Color Control Register 2 = (X – 0.75) × 128
where X = Scaling factor for V
e.g., Scale V by 1.2
Color Control Register 2 = (1.2 – 0.75) × 128 = 57.6 = 111001
(rounded to the nearest integer)
HUE CONTROL REGISTER (HCR)
(Address (SR5–SR0) = 20H)
The hue control register is an 8-bit-wide register used to adjust
the hue on the composite and chroma outputs. Figure 65 shows
the operation under control of this register.
HCR BIT DESCRIPTION
Hue Adjust Value (HCR7–HCR0)
These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier with
respect to the phase of the subcarrier during the color burst.
The ADV7172/ADV7173 provides a range of ± 22° in incre-
ments of 0.17578125°. For normal operation (zero adjustment)
this register is set to 80 Hex. FFHex and 00Hex represent the
upper and lower limit (respectively) of adjustment attainable.
Hue Adjust = (0.17568125 × [HCR7 – HCR0 – 128]).
CC17 CC16 CC15 CC14
CC13
CC12 CC11 CC10
CC15–CC10
U SCALAR VALUE
CC17–CC16
ZERO SHOULD
BE WRITTEN
TO THESE BITS
CC27 CC26 CC25 CC24 CC23 CC22 CC21 CC20
CC25–CC20
V SCALAR VALUE
CC27–CC26
ZERO SHOULD
BE WRITTEN
TO THESE BITS
Figure 64. Color Control Registers
HCR7 HCR6 HCR5 HCR4 HCR3 HCR2 HCR1 HCR0
HCR7–HCR0
HUE ADJUST VALUE
Figure 65. Hue Control Register
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

ADV7173KSTZ-REEL

Mfr. #:
Buy ADV7173KSTZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Video ICs PAL/NTSC Encoder w/ 6 DAC 10B
Lifecycle:
New from this manufacturer.
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