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PCU9661B,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 10 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
7.5.1 Channel registers
7.5.1.1 STATUS2_[n] — Transaction status registers
STATUS2_[n] is an 8-bit 64 read-only registers that provide status information for a
given transaction. Only the 2 lower bits are used; the top bits will always read 0. The
controller will auto-clear the STATUS2_[n] registers at each START of a sequence when
FRAMECNT = 1 and only at the first START when FRAMECNT 1.
Each register byte can be accessed by direct addressing so that the host can choose to
read the status on one or more individual transactions without having to read all
64 status bytes.
Remark: When STATUS2_[n] = 00h, no interrupt is requested and the transaction is in the
Done/Idle state.
During program execution, the TR and TA bits behave as follows:
Example, we are to transfer 3 transactions in a sequence. All initialization is completed
(loading of SLA, TRANCONFIG, DATA) and device is ready for serial transfer.
Before the STA bit is set, the STATUS2_[n] register will contain:
STATUS2_[0] = 0
STATUS2_[1] = 0
STATUS2_[2] = 0
STATUS2_[3] = 0
:
After STA is set:
STATUS2_[0] = 2
STATUS2_[1] = 1
STATUS2_[2] = 1
STATUS2_[3] = 0
:
Since there is no timing requirement in setting the STA bit after the initialization, the device
will update the first status when the STA bit is set and will always go from 0 to 2 (Idle to
Transaction active).
Table 4. STATUS2_[n] - Transaction status code register bit description
Bit Symbol Description
7:2 ST[7:2] always reads 0000 00
1 TA Transaction active. When 1, the transaction is currently active on the serial bus.
No interrupt is requested.
0 TR Transaction ready. When 1, a transaction is loaded in the buffer and waiting to be
executed. No interrupt is requested.
PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 11 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
7.5.1.2 CONTROL — Control register
CONTROL is an 8-bit register. The STO bit is affected by the bus controller hardware: it is
cleared when a STOP condition is present on the I
2
C-bus.
Table 5. CONTROL - Control register bit description
Address: Channel 2 = E0h.
Legend: * reset value
Bit Symbol Access Value Description
7 STOSEQ R/W Stop sequence bit.
1 When the STOSEQ bit is set while the channel is active, a
STOP condition will be transmitted immediately following
the end of the current sequence being transferred on the
I
2
C-bus. No further buffered transactions will be carried out
and the channel will return to the idle state. Normal error
reporting will occur up until the last bit. When a STOP
condition is detected on the bus, the hardware clears the
STOSEQ flag.
0* When STOSEQ is reset, no action will be taken.
6 STA R/W The START flag.
1 The STA bit is set to begin a sequence.
The STA bit may be set only at a valid idle state. The
controller will reset the bit under the following conditions:
• A sequence is done and FRAMECNT = 1.
• A sequence loop is done and FRAMECNT > 1.
• The STOSEQ bit is set, FRAMECNT = 0, and the
current sequence is done.
• The STOSEQ bit is set, FRAMECNT > 1, and the
current sequence is done.
• The STO bit is set and the current byte transaction is
done. This bit cannot be set if the CHEN bit is 0.
0* When the STA bit is reset, no START condition will be
generated.
5 STO R/W The STOP flag.
1 When the STO bit is set while the channel is active, a STOP
condition will be transmitted immediately following the
current data or slave address byte being transferred on the
I
2
C-bus. No further buffered transactions will be carried out
and the channel will return to the idle state. Normal error
reporting will occur up until the last bit.
When a STOP condition is detected on the bus, the
hardware clears the STO flag.
0* When the STO bit is reset, no action will be taken.
4 TP R/W Trigger polarity bit. Cannot be changed while channel is
active.
1 Trigger will be detected on a falling edge.
0* Trigger will be detected on a rising edge.
PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 12 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
Remark: Due to a small latency between setting the STA bit and the ability to detect a
trigger pulse, if the STA bit is set simultaneously to an incoming trigger pulse, the pulse
will be ignored and the controller will wait for the next trigger to send the START.
If the STO or STOSEQ bit are set at anytime while the STA bit is 0, then no action will be
taken and the write to these bits is ignored.
Remark: STO has priority over STOSEQ.
3 TE R/W Trigger Enable (TE) bit controls the trigger input used for
frame refresh. TE cannot be changed while channel is
active. When the trigger input is enabled, the trigger will
override the contents of the FRAMECNT register and will
start triggering when STA bit is set. Thereafter, when a
trigger tick is detected, the controller will issue a START
command and the stored sequence will be transferred on
the serial bus.
1 When TE = 1, the sequence is controlled by the Trigger
input.
0* When TE = 0, the trigger inputs are ignored.
2 BPTRRST W 1 Resets auto increment pointers for BYTECOUNT. Reads
back as 0.
1 AIPTRRST W 1 Resets auto increment pointers for SLATABLE and
TRANCONFIG. The DATA register auto-increment pointer
will be set to the value that corresponds to TRANSEL and
TRANOFS registers. Reads back as 0.
Remark: To reset the data pointer, write 00h to TRANSEL.
0 - W 0 Reserved. User must write 0 to this bit.
Table 5. CONTROL - Control register bit description
…continued
Address: Channel 2 = E0h.
Legend: * reset value
Bit Symbol Access Value Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

PCU9661B,118

Mfr. #:
Buy PCU9661B,118
Manufacturer:
NXP Semiconductors
Description:
Universal Bus Functions PARALLEL BUS TO FM+I2C BUS CONTRLLR
Lifecycle:
New from this manufacturer.
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