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PCU9661B,118

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PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 13 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
[1] Loop Idle is defined as the time elapsed from a STOP to the START of the next sequence while STA = 1.
[2] Channel Active is defined by the CTRLSTATUS[5:3] bits.
Table 6. CONTROL register bits STA, STO, STOSEQ operation/behavior
Channel state
(initialization steps)
Next write action by host Results
FRAMECNT TE STA STO STOSEQ
Idle (reset, TRANCONFIG,
SLATABLE, DATA, STA = 0)
1 0 0 X X No action.
1 0 1 X X START transmitted on serial bus followed by
sequence stored in buffer.
Active (reset, load
TRANCONFIG, SLATABLE,
DATA, STA = 1
1 0 X 0 X No change; cannot write STA while active.
1 0 X 1 X When the STO bit is set:
1. A STOP is sent after the end of ACK
cycle of the current byte and BYTECNT
is updated.
The SD bits will be set.
REFRATE Loop idle (reset,
load TRANCONFIG,
SLATABLE, DATA STA = 1)
[1]
1 0 0 X X No action.
1 0 X 0 1 Channel will go immediately to the inactive
state and SD and FLD bits will be set.
[2]
1 0 X 1 X Channel will go immediately to the inactive
state and SD and FLD bits will be set.
[2]
REFRATE Loop active (reset,
load, TRANCONFIG,
SLATABLE, DATA, STA = 1)
1 0 X 0 0 No action.
1 0 X 0 1 STOP at end of current frame. The SD and
FLD bits will be set.
1 0 X 1 X When the STO bit is set:
1. A STOP is sent after the end of ACK
cycle of the current byte and BYTECNT
is updated.
The SD and FLD bits will be set.
Trigger Loop Idle (reset, load
TRANCONFIG, SLATABLE,
DATA, STA = 1)
X 1 0 X X No action.
X 1 X 0 1 STOP at end of current frame. The SD and
FLD bits will be set.
X 1 X 1 X When the STO bit is set:
1. A STOP is sent after the end of ACK
cycle of the current byte and the
BYTECNT is updated.
The SD and FLD bits will be set.
Trigger Loop active (reset, load
TRANCONFIG, SLATABLE,
DATA, STA = 1)
X 1 X 0 0 No action.
X 1 X 0 1 Channel will go immediately to the inactive
state and SD and FLD bits will be set.
[2]
X 1 X 1 X Channel will go immediately to the inactive
state and SD and FLD bits will be set.
[2]
PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 14 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
7.5.1.3 CHSTATUS — Channel status register
CHSTATUS is an 8-bit read-only register that provides status information for the serial
channel. All these status drive the INT
pin active LOW. To clear the channel interrupt
request, you must read the CHSTATUS register. The BE interrupt is cleared by reading
the CTRLSTATUS register.
After the CHSTATUS register is cleared, only new errors or status updates will cause the
CHSTATUS bits to be set.
[1] Bits [5:1] always read as logic 0.
FE - Frame Error bit: This bit indicates that the time required to send the sequence
exceeds the refresh rate programmed in the REFRATE register or the time between
trigger ticks. Solving frame errors include programming longer refresh rates, speeding up
the bus frequency, shortening the amount of bytes sent/received in the sequence, or
increasing the time between trigger ticks. If the frame error is masked by the FEMSK, the
device will continue to transmit transactions until the end of the sequence without
re-starting the sequence even if new triggers are detected. The total number of sequences
transmitted will be the number stored in the FRAMECNT register. Once a complete
sequence is transmitted, a new sequence will initiate when a subsequent trigger appears.
The FE flag will be held HIGH and sequences will still be transmitted unless CHSTATUS is
read. If the frame error is unmasked, the sequence will be aborted at the next logical
stopping point, a STOP transmitted and an interrupt will be generated. The FE bit is set
after the STOP is detected on the bus.
Table 7. CHSTATUS - Channel and buffer status codes register bit description
Address: Channel 2 = E1h.
Bit Symbol Description
7 SD Sequence Done. The sequence loaded in the buffer was sent and STOP issued
on the serial bus.
6 FLD Frame Loop Done. The FRAMECNT value has been reached. A STOP has been
issued on the bus.
5:1 - Reserved.
0 FE Frame Error detected. The time required to send the sequence exceeds refresh
rate programmed to the REFRATE register or the time between trigger ticks.
PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 15 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
7.5.1.4 INTMSK — Interrupt mask register
Through the INTMSK register, there is the option to manage which states generate an
interrupt, allowing more control from the host on the transaction. The interrupt mask
applies to all transactions on the channel. A bit set to 1 indicates that the mask is active.
The INTMSK register default is all interrupts are un-masked (00h).
a. Sequence fully executed within the period programmed in REFRATE register
This condition causes a frame error and the FE bit to be set.
b. Sequence exceeds period programmed in REFRATE register, FEMSK = 0
c. Sequence exceeds period programmed in REFRATE register, FEMSK = 1
Fig 3. Frame Error detection
002aaf247
sequence A sequence A sequence A
10 ms 10 ms 10 ms
time
002aaf627
sequence B
10 ms 10 ms 10 ms
time
frame error detected, data not sent after FE
002aaf628
sequence C
10 ms 10 ms 10 ms
time
frame error detected, FEMSK = 1, data sent after FE
sequence C
Table 8. INTMSK - Interrupt mask register bit description
Address: Channel 0 = C2h; Channel 1 = D2h; Channel 2 = E2h.
Bit Symbol Description
7 SDMSK Sequence Done Mask. The end of sequence interrupt will not be generated.
6 FLDMSK Frame loop done mask. A frame loop done interrupt will not be generated. The
controller will enter the idle state.
5:1 - reserved
0 FEMSK Frame Error Mask. A frame error interrupt will not be generated.
Remark: Use caution and good judgement when using this mask.
Unexpected/erratic behavior may result in the slave devices.
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PCU9661B,118

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Buy PCU9661B,118
Manufacturer:
NXP Semiconductors
Description:
Universal Bus Functions PARALLEL BUS TO FM+I2C BUS CONTRLLR
Lifecycle:
New from this manufacturer.
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