PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 30 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
8.2 Stopping a sequence
If the host needs to stop the execution of a sequence, it should set the STO bit in the
CONTROL register. For write transactions, the host will issue a STOP after the
acknowledge cycle of the current byte being transferred on the serial bus. No interrupts
will be generated and all the status registers will be up to date. The Sequence Done bit
(SD) will be set to indicate to the host that the STOP condition was completed and the bus
is idle. The Sequence Done and the Frame Loop Done will be set if the channel is in Loop
mode (FRAMECNT 1) and a STO or STOSEQ bit is set.
If the host issues a STOP (by setting the STO) in the middle of a sequence followed by a
START (by setting the STA), then the controller will re-send the sequence from the
beginning, not from the point where the sequence was last stopped.
8.3 Looping a sequence
A sequence can be set to automatically loop several times using the FRAMECNT and one
of the following:
• The REFRATE register. The REFRATE register contains the value of the refresh rate
which is timing required between the START of two sequences. The refresh rate is
derived from the internal clock of the bus controller. If the REFRATE is programmed to
00h, the sequences will be looped back-to-back.
• Trigger enable (TE) bit. When TE is set, the refresh rate is controlled by the external
trigger input and the contents of the REFRATE registers is ignored. There is no
maximum timing requirement for the trigger interval.
The FRAMECNT register sets the number of times the sequence will be repeated. A
frame is defined as a sequence associated with its respective refresh rate. As described
above, the frame refresh rate is determined by the REFRATE register or an external
trigger source.
During looping, there is no host intervention required and all status and error reporting
remains active. The SD (Sequence Done) bit can be masked to avoid getting interrupted
each time a frame is completed while the other error reporting bits remain unmasked. In
this manner, normal transactions can run without host intervention and errors will be
reported at the STOP of the current byte where the error occurred.
Once the FRAMECNT values is reached, the FLD bit in the CHSTATUS register is set and
no further transactions will be executed and the channel will go to the idle state. The FLD
interrupt can be masked with the FLDMSK bit in the CTRLINTMSK register. The host can
poll the CTRLSTATUS register to check if the channel is active (looping) or if it is idle.
For indefinite or long term looping the host can do the following:
1. A sequence can be set to loop indefinitely by setting the FRAMECNT register to 00h.
Each frame will be sent out following the REFRATE settings or the Trigger input if the
TE bit is set. To end the Loop mode, the host sets the STO or STOSEQ bits in the
CONTROL register.
2. A frame will be sent out continuously and back-to-back if FRAMECNT and REFRATE
are set to 00h. To end the Loop mode, the hose sets the STO or STOSEQ bits in the
CONTROL register.
