PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 27 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
When a sequence is in progress, no interrupts are generated unless there is an error
when a transaction is conducted. The host will only receive an interrupt when the
sequence is done. The PCU9661 will behave as a Master Transmitter regardless of the
direction bits specified in the SLATABLE. The host has the ability to update the data buffer
while the controller carries on the remaining transactions in the sequence.
8.1 Sequence execution
Sequences can only be of one type:
• Write transactions, where the PCU9661 will behave as a Master Transmitter
Data transfers in one direction are shown in Figure 9
. This figure contains the following
abbreviations:
S — START condition
SLA — 7-bit slave address
W — Write bit (LOW level at SDA)
A
— Not acknowledge bit (HIGH level at SDA)
Data — 8-bit data byte
P — STOP condition
In Figure 9
, circles are used to indicate when a bit is set in the CHSTATUS register. A
channel interrupt is not requested when CHSTATUS = 00h and the INT
pin is not asserted
when the interrupt is masked (see Section 7.5.2.2
).
For a successful sequence execution, all three components mentioned above must exist
in the memory and must be correctly set up. There are not safeguards against
programming incorrect transaction sizes, data buffer lengths, or direction bits. If the
transaction length is set to 00h, then only the slave address with direction bit will be
transmitted.
Once the host has configured the serial port and programmed the TRANCONFIG (number
of slaves and bytes per slave), the SLATABLE (slave addresses), TRANSEL (transaction
data buffer selection) and the TRANOFS (byte offset selection) and loaded the serial data
into the DATA buffer, the sequence is ready to be transmitted.
To send the sequence, the host will set the STA bit in the CONTROL register and the
controller will immediately send a START on the serial bus. Then, the transactions will be
carried out in the order they appear in the SLATABLE, each being separated by a
ReSTART command.
If the interrupts are unmasked, the serial transfer will be conducted without generating
interrupts in between transactions. Once all transactions are successfully completed, the
controller will generate a STOP, the Sequence Done bit (SD) will be set in the CHSTATUS
and an interrupt will be generated.
Once all transactions are completed, the controller will generate a STOP and the
Sequence Done bit (SD) will be set in the CHSTATUS and an interrupt will be generated.
If the host wants to poll the PCU9661, it can mask all registers including the SD bit and
read the CTRLSTATUS, CHSTATUS, STATUS2_[n], and/or the CONTROL registers to
determine the state of the controller.
