PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 40 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
14. Dynamic characteristics
[1] Parameters are valid over specified temperature and voltage range.
[2] All voltage measurements are referenced to ground (V
SS
). For testing, all inputs swing between 0 V and 3.0 V with a transition time of
5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figure 21
and Figure 23.
[3] Test conditions for outputs: C
L
=50pF; R
L
= 500 , except open-drain outputs.
Test conditions for open-drain outputs: C
L
=50pF; R
L
=1k pull-up to V
DD
.
[4] Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.
[5] Upon reset, the full delay will be the sum of t
rst
and the RC time constant of the SDA and SCL bus.
Table 32. Dynamic characteristics (3.3 volt)
[1][2][3]
V
DD
=3.3V
0.3 V; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Initialization timing
t
init(po)
power-on initialization time V
DD
3.0 V - - 650 s
t
init
initialization time channel initialization time from
Channel Software Reset
--70s
controller initialization time from
POR, RESET
, or Global Software
Reset inactive
--650s
RESET
timing
t
w(rst)
reset pulse width 4 - - s
t
rst
reset time
[4][5]
1.5 - - s
INT
timing
t
as(int)
interrupt assert time - - 500 ns
t
das(int)
interrupt de-assert time - - 100 ns
TRIG timing
t
w(trig)
trigger pulse width HIGH or LOW 100 - - ns
Bus timing (see Figure 21
and Figure 23)
t
su(A)
address set-up time to RD, WR LOW 0 - - ns
t
h(A)
address hold time from RD, WR LOW 14 - - ns
t
su(CE_N)
CE set-up time to RD, WR LOW 0 - - ns
t
h(CE_N)
CE hold time from RD, WR LOW 0 - - ns
t
w(RDL)
RD LOW pulse width 40 - - ns
t
w(WRL)
WR LOW pulse width 40 - - ns
t
d(DV)
data valid delay time after RD and CE LOW - - 45 ns
t
d(QZ)
data output float delay time after RD or CE HIGH - - 7 ns
t
su(Q)
data output set-up time before WR HIGH 5 - - ns
t
h(Q)
data output hold time after WR HIGH 2 - - ns
t
w(RDH)
RD HIGH pulse width 40 - - ns
t
w(WRH)
WR HIGH pulse width 40 - - ns
