PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 31 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
8.3.1 Looping with REFRATE control
When using the REFRATE register (TE bit is 0) the refresh rate timing is controlled
internally. Once the STA bit is set, the START command will be immediately sent on the
serial bus followed by the sequence. Thereafter, the controller will issue a START
command followed by the stored sequence every time the REFRATE value is reached. It
is important to program enough time in the REFRATE to allow a complete sequence to
reach the Sequence Done state. If the refresh rate is not long enough, the Frame Error
(FE) bit will be set and an interrupt will be generated. The FE bit is maskable, however,
masking the FE bit may yield undesired results on the serial interface. If the FE bit is
masked, the Loop mode will continue to operate and the FE flag will remain set. To exit
the Loop mode, the STO or the STOSEQ bit should be set.
8.3.2 Looping with Trigger control
The PCU9661 has one trigger input. The trigger enable (TE) bit in the CONTROL register
is used to control the use of external triggering. Once enabled, the trigger will override the
contents of the REFRATE register, and will start triggering when the STA bit is set.
Therefore, a significant time delay can occur between setting the STA bit and the
detection of a trigger. When a trigger edge is detected, the controller will issue a START
command and the stored sequence will be transferred on the serial bus. The trigger will
control the timing of the frame, therefore, enough time should be allowed by the trigger to
allow the sequence to reach the Sequence Done state.
If a trigger edge is detected while a sequence is actively being transmitted on the bus, the
Frame Error (FE) bit will be set and an interrupt will be generated. The FE bit is maskable,
however, masking the FE bit may yield undesired results on the serial interface. If the FE
bit is masked, the Loop mode will continue to operate and the FE flag will remain set. The
polarity of the trigger edge detect is controlled by the TP bit in the CONTROL register. To
exit the Trigger mode, the STO or the STOSEQ bit should be set.
8.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset holds the PCU9661 in a reset
condition until V
DD
has reached V
POR
. At this point, the reset condition is released and the
PCU9661 goes to the power-up initialization phase where the following operations are
performed:
1. The oscillator and PLL will be re-initialized.
2. Internal register initialization is performed.
3. The memory space will be zeroed out.
The complete power-up initialization phase takes t
rst
to be performed. During this time,
writes to the PCU9661 through the parallel port are ignored. However, the parallel port
can be read. This allows the device connected to the parallel port of the PCU9661 to poll
the CTRLRDY register.
