PCU9661 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 12 September 2011 22 of 52
NXP Semiconductors
PCU9661
Parallel bus to 1 channel UFm I
2
C-bus controller
7.5.1.14 MODE — I
2
C-bus mode register
MODE is a read/write register. It contains the control bits that select the bus recovery
options, and the correct timing parameters. Timing parameters involved with AC[1:0] are
t
BUF
, t
HD;STA
, t
SU;STA
, t
SU;STO
, t
HIGH
, t
LOW
. The auto recovery and bus recovery bits are
contained in this register. They control the bus recovery sequence.
Remark: CHEN bit value must be changed only when the I
2
C-bus is idle.
Remark: The AC[1:0] are read-only bits. The UFm channel AC parameters are controlled
internally.
7.5.1.15 PRESET — I
2
C-bus channel parallel software reset register
PRESET is an 8-bit write-only register. Programming the PRESET register allows the user
to reset the channel under software control. The software reset is achieved by writing two
consecutive bytes to this register. The first byte must be A5h while the second byte must
be 5Ah. The writes must be consecutive and the values must match A5h and 5Ah. If this
sequence is not followed as described, the reset is aborted.
The PRESET resets state-machines, registers, and buffer pointers to the default values,
zeroes the TRANCONFIG, SLATABLE, BYTECOUNT, and DATA arrays of the respective
channel and will not reset the entire chip. The parallel bus remains active while a software
reset is active. The user can read the PRESET register to determine when the reset has
completed, PRESET returns all 1s when the reset is active and all 0s when complete.
Table 23. MODE - I
2
C-bus mode register bit description
Address: Channel 2 = EDh.
Bit Symbol Description
7 CHEN Channel Enable bit. R/W.
0: Channel is disabled, SCL and SDA high-impedance, USDA and USCL driven
HIGH. All registers are accessible for setup and configuration, however a
sequence cannot be started if the CHEN bit is 0 (STA cannot be set).
1 (default): Channel is enabled.
6:2 - Reserved.
UFm Channel 2
1:0 AC[1:0] I
2
C-bus mode selection to ensure proper timing parameters (see Table 33).
AC[1:0] = 00: Reserved.
AC[1:0] = 01: Reserved.
AC[1:0] = 10: Reserved.
AC[1:0] = 11 (default): Ultra Fast-mode AC parameters selected. Read-only
bits.
Table 24. PRESET - I
2
C-bus channel parallel software reset register bit description
Address: Channel 2 = EFh.
Bit Symbol Description
7:0 PRESET[7:0] Read/Write register used during an I
2
C-bus channel parallel reset command.
