26
INDUSTRIAL TEMPERATURE RANGE
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
I
2
C SERIAL INTERFACE CONTROL
The I
2
C interface permits the configuration of the IDT5T9821. The
IDT5T9821 is a read/write slave device meeting Philips I
2
C bus specifications.
The I
2
C bus is controlled by a master device that generates the serial clock
SCLK, controls bus access, and generates the START and STOP conditions
while the device works as a slave. Both master and slave can operate as a
transmitter and receiver but the master device determines which mode is
activated.
BUS CONDITIONS
Data transfer on the bus can only be initiated when the bus is not busy.
During data transfer, the data line (SDA) must remain stable whenever the
clock line (SCLK) is high. Changes in the data line while the clock line is high
will be interpreted by the device as a START or STOP condition. The following
bus conditions are defined by the I
2
C bus protocol and are illustrated in figure
1.
NOT BUSY
Both the data (SDA) and clock (SCLK) lines remain high to indicate the bus
is not busy.
START DATA TRANSFER
A high to low transition of the SDA line while the SCLK input is high indicates
a START condition. All commands to the device must be preceded by a START
condition.
STOP DATA TRANSFER
A low to high transition of the SDA line while SCLK is held high indicates a
STOP condition. All commands to the device must be followed by a STOP
condition.
DATA VALID
The state of the SDA line represents valid data if the SDA line is stable for
the duration of the high period of the SCLK line after a START condition occurs.
The data on the SDA line must be changed only during the low period of the
SCLK signal. There is one clock pulse per data bit. Each data transfer is initiated
by a START condition and terminated with a STOP condition.
ACKNOWLEDGE
When addressed, the receiving device is required to generate an
Acknowledge after each byte is received. The master device must generate
an extra clock pulse to coincide with the Acknowledge bit. The acknowledging
device must pull the SDA line low during the high period of the master
acknowledge clock pulse. Setup and hold times must be taken into account.
Address A0 is the read/write bit and is set to ‘0’ for writes and ‘1’ for reads.
The ADDR0 and ADDR1 tri-level pins allow the last three bits of the 7-bit
address to be defined by the user.
WRITE OPERATION
(see I
2
C Interface Definition for ProgWrite)
To initiate a write operation (ProgWrite), the read/write bit is set to ‘0’. During
the write operation, the first two bytes transferred must be the Device Address
followed by the Command Code. The internal programming registers of the
device ignore these first two bytes. The subsequent bytes are the Data Bytes,
which total twelve. All twelve Data Bytes must be written into the device during
the write operation in order for the internal programming registers to be
updated. If a STOP condition is generated before the 12
th
Data Byte, the internal
programming registers will remain unchanged to prevent an invalid PLL
configuration. An Acknowledge by the device between each byte must occur
before the next byte is sent. After the transfer of the 12
th
Data Byte, an
Acknowledge signal will be sent to the bus master after which it will generate
a STOP condition. Once the STOP condition has occurred, the internal
programming registers of the device will be updated.
READ OPERATION
(see I
2
C Interface Definition for ProgRead)
To initiate a read operation (ProgRead), the read/write bit is set to ‘1’. During
the read operation, there will be a total of fourteen data bytes returned following
an Acknowledge of the device address. The first two data bytes are the ID Byte
and a Reserved Byte, in that order. The subsequent bytes are the same twelve
Data Bytes that were written during the write operation. The read back can
be terminated at any time by issuing a STOP condition.
I
2
C ID BYTE
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
00000101
I
2
C ADDRESS
A7 A6 A5 A4 A3 A2 A1
1101XX X
ADDR1 ADDR0 A3 A2 A1
LOW LOW 0 0 0
LOW MID 0 0 1
LOW HIGH 0 1 0
MID LOW 0 1 1
MID MID 1 0 0
MID HIGH 1 0 1
HIGH LOW 1 1 0
HIGH MID 1 1 1
HIGH HIGH 1 1 0
JTAG/ I
2
C SERIAL CONFIGURATIONS:
VCO FREQUENCY SELECT
Bit 60 Min. Max.
0 50Mhz 125MHz
1 100MHz 250Mhz
I
2
C BUS OPERATION
The IDT5T9821 I
2
C interface supports Standard-Mode (100kHz) and Fast-
Mode (400kHz) data transfer rates. Data is transferred in bytes in sequential
order from the lowest to highest byte. After generating a START condition, the
bus master broadcasts a 7-bit slave address followed by a read/write bit.
