5
INDUSTRIAL TEMPERATURE RANGE
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
PIN DESCRIPTION, CONTINUED
Symbol I/O Type Description
REF_SEL I LVTTL
(1)
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.
nsOE I LVTTL
(1)
Synchronous output enable/disable. Each outputs's enable/disable state can be controlled either with the nsOE pin or through JTAG
or I
2
C programming, corresponding bits 52 - 56. When the nsOE is HIGH or the corresponding Bit (52 - 56) is 1, the output will be
synchronously disabled. When the nsOE is LOW and the corresponding Bit (52 - 56) is 0, the output will be enabled. (See JTAG/I
2
C
Serial Configuration table.)
QFB O Adjustable
(2)
Feedback clock output
QFB O Adjustable
(2)
Complementary feedback clock output
nQ O Adjustable
(2)
Clock outputs
nQ O Adjustable
(2)
Complementary clock outputs
PLL_EN I LVTTL
(1)
PLL enable/disable control. The PLL's enable/disable state can be controlled either with the PLL_EN pin or through JTAG or I
2
C
programming, corresponding Bit 57. When PLL_EN is HIGH or the corresponding Bit 57 is 1, the PLL is disabled and REF
[1:0] goes
to all outputs. When PLL_EN is LOW and the corresponding Bit 57 is 0, the PLL will be active.
PD I LVTTL
(1)
Power down control. When PD is LOW, the inputs are disabled and internal switching is stopped. The OMODE pin in conjunction
with the corresponding Bit 59 selects whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH or Bit 59 is 1,
Bit 58 determines the level at which the outputs stop. When Bit 58 is 0/1, the nQ and QFB are stopped in a HIGH/LOW state, while
the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and Bit 59 is 0, the outputs are tri-stated. Set PD HIGH
for normal operation. (See JTAG/I
2
C Serial Configuration table.)
LOCK O LVTTL PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to
the inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK pin, please see AN237.)
OMODE I LVTTL
(1)
Output disable control. Used in conjunction with nsOE and PD. The outputs' disable state can be controlled either with the OMODE
pin or through JTAG or I
2
C programming, corresponding Bit 59. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated and Bit 58 will determine the level at which the outputs stop. When Bit 58 is 0/1, the nQ and QFB are stopped
in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding bit
59 is 0, the outputs disable state will be the tri-state. (See JTAG/I
2
C Serial Configurations tables.)
TRST/SEL I/I LVTTL/ TRST- Active LOW input to asynchronously reset the JTAG boundary-scan circuit.
LVTTL
(4,5)
SEL - Select programming interface control for the dual-function pins. When HIGH, the dual-function pins are set for JTAG programming.
When LOW, the dual-function pins are set for I
2
C programming and the JTAG interface is asynchronously placed in the Test Logic Reset
state.
TDO/ADDR1 O/I LVTTL/ TDO - Serial data output pin for instructions as well as test and programming data. Data is shifted in on the falling edge of TCLK. The
pin is tri-stated if data is not being shifted out of the device.
ADDR1 - Used to define a unique I
2
C address for this device. Only for I
2
C programming. (See JTAG/I
2
C Serial Interface Description.)
TMS/ADDR0 I/I LVTTL/ TMS - Input pin that provides the control signal to determine the transitions of the JTAG TAP controller state machine. Transitions within
the state machine occur at the rising edge of TCLK. Therefore, TMS must be set up before the rising edge of TCLK. TMS is evaluated
on the rising edge of TCLK.
ADDR0 - Used to define a unique I
2
C address for this device. Only for I
2
C programming. (See JTAG/I
2
C Serial Interface Description.)
TCLK/SCLK I/I LVTTL/ TCLK - The clock input to the JTAG BST circuitry.
SCLK - Serial clock for I
2
C programming
TDI/SDA I/I LVTTL/ TDI - Serial input pin for instructions as well as test and programming data. Data is shifted in on the rising edge of TCLK.
SDA - Serial data (see JTAG/I
2
C Serial Description table)
VDDQN PWR Power supply for each pair of outputs. When using 2.5V LVTTL, 1.8V LVTTL, HSTL, or eHSTL outputs, VDDQN should be set to its
corresponding outputs (see Front Block Diagram). When using 2.5V LVTTL outputs, VDDQN should be connected to VDD.
VDD PWR Power supply for phase locked loop, lock output, inputs, and other internal circuitry
GND PWR Ground
3-Level
(3,4,5)
3-Level
(3,4,5)
LVTTL
(4,5)
LVTTL
(4,5)
NOTES:
1. Pins listed as LVTTL inputs can be configured to accept 1.8V or 2.5V signals through the use of the I
2
C/JTAG programming, bit 61. (See JTAG/I
2
C Serial Description.)
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQN voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
4. The JTAG (TDO, TMS, TCLK, and TDI) and I
2
C (ADDR1, ADDR0, SCLK, and SDA) signals share the same pins (dual-function pins) for which the TRST/SEL pin will select between
the two programming interfaces.
5. JTAG and I
2
C pins accept 2.5V signals. The JTAG input pins (TMS, TCLK, TDI, TRST) will also accept 1.8V signals.
