IDT5T9821NLI Datasheet IDT5T9821NLI, IDT5T9821NLGI, IDT5T9821NLGI8 | P31-P33

INDUSTRIAL TEMPERATURE RANGE

IDT5T9821

EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER

NOTES:

1. Five consecutive TCLK cycles with TMS = 1 will reset the TAP.

2. TAP controller must be reset before normal PLL operations can begin.

Refer to the IEEE Standard Test Access Port Specification (IEEE Std.1149.1)

for the full state diagram

All state transitions within the TAP controller occur at the rising edge of

theTCLK pulse. The TMS signal level (0 or 1) determines the state progression

that occurs on each TCLK rising edge. The TAP controller takes precedence

over the PLL and must be reset after power up of the device. See TRST

description for more details on TAP controller reset.

Test-Logic-Reset All test logic is disabled in this controller state enabling

the normal operation of the IC. The TAP controller state machine is designed

in such a way that, no matter what the initial state of the controller is, the Test-

Logic-Reset state can be entered by holding TMS at high and pulsing TCLK

five times. This is the reason why the Test Reset (TRST) pin is optional.

Run-Test-Idle In this controller state, the test logic in the IC is active only

if certain instructions are present. For example, if an instruction activates the

self test, then it will be executed when the controller enters this state. The test

logic in the IC is idles otherwise.

Select-DR-Scan This is a controller state where the decision to enter the

Data Path or the Select-IR-Scan state is made.

Select-IR-Scan This is a controller state where the decision to enter the

Instruction Path is made. The Controller can return to the Test-Logic-Reset

state otherwise.

Capture-IR In this controller state, the shift register bank in the Instruction

The last two significant bits are always required to be “01”.

Shift-IR In this controller state, the instruction register gets connected

between TDI and TDO, and the captured pattern gets shifted on each rising

edge of TCLK. The instruction available on the TDI pin is also shifted in to the

instruction register.

Exit1-IR This is a controller state where a decision to enter either the Pause-

IR state or Update-IR state is made.

Pause-IR This state is provided in order to allow the shifting of instruction

Exit2-DR This is a controller state where a decision to enter either the Shift-

IR state or Update-IR state is made.

Update-IR In this controller state, the instruction in the instruction register

is latched in to the latch bank of the Instruction Register on every falling edge

of TCLK. This instruction also becomes the current instruction once it is latched.

Capture-DR In this controller state, the data is parallel loaded in to the data

registers selected by the current instruction on the rising edge of TCLK.

Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These

controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and

Update-IR states in the Instruction path.

TAP Controller State Diagram

Test-Logic

Reset

Run-Test/

Idle

Select-

DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-

IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

INDUSTRIAL TEMPERATURE RANGE

IDT5T9821

EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER

THE INSTRUCTION REGISTER

The Instruction register allows an instruction to be shifted in serially into the

processor at the rising edge of TCLK.

The Instruction is used to select the test to be performed, or the test data

latched at the completion of the shifting process when the TAP controller is at

Update- IR state.

The instruction register must contain 4 bit instruction register-based cells

which can hold instruction data. These mandatory cells are located nearest the

serial outputs they are the least significant bits.

TEST DATA REGISTER

The Test Data register contains three test data registers: the Bypass, the

Boundary Scan register and Device ID register.

These registers are connected in parallel between a common serial input

and a common serial data output.

The following sections provide a brief description of each element. For a

complete description, refer to the IEEE Standard Test Access Port Specification

(IEEE Std. 1149.1-1990).

TEST BYPASS REGISTER

The register is used to allow test data to flow through the device from TDI

to TDO. It contains a single stage shift register for a minimum length in serial

path. When the bypass register is selected by an instruction, the shift register

stage is set to a logic zero on the rising edge of TCLK when the TAP controller

is in the Capture-DR state.

The operation of the bypass register should not have any effect on the

operation of the device in response to the BYPASS instruction.

THE BOUNDARY-SCAN REGISTER

The Boundary Scan Register allows serial data TDI be loaded in to or read

out of the processor input/output ports. The Boundary Scan Register is a part

of the IEEE 1149.1-1990 Standard JTAG Implementation.

THE DEVICE IDENTIFICATION REGISTER

The Device Identification Register is a Read Only 32-bit register used to

specify the manufacturer, part number and version of the processor to be

determined through the TAP in response to the IDCODE instruction.

IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is

dropped in the 11-bit Manufacturer ID field.

For the IDT5T9821, the Part Number field is 0X3A7.

JTAG INSTRUCTION REGISTER

The Instruction register allows instruction to be serially input into the device

when the TAP controller is in the Shift-IR state. The instruction is decoded to

perform the following:

• Select test data registers that may operate while the instruction is current.

The other test data registers should not interfere with chip operation and the

selected data register.

IR (3) IR (2) IR (1) IR (0) Instruction Function

0 0 0 0 EXTEST Select boundary scan register

0 0 0 1 SAMPLE/PRELOAD Select boundary scan register

0 0 1 0 IDCODE Select chip identification data register

0 0 1 1 Reserved

0 1 0 0 PROGWRITE Writing to the volatile programming registers

0 1 0 1 PROGREAD Reading from the volatile programming registers

0 1 1 0 PROGSAVE Saving the contents of the volatile programming registers to the EEPROM

0 1 1 1 PROGRESTORE Loading the EEPROM contents into the volatile programming registers

1 0 0 0 CLAMP JTAG

1 0 0 1 HIGHZ JTAG

1 0 1 X BYPASS Select bypass register

1 1 X X BYPASS Select bypass register

JTAG INSTRUCTION REGISTER DECODING

• Define the serial test data register path that is used to shift data between

TDI and TDO during data register scanning.

The Instruction Register is a 4-bit field (i.e.IR3, IR2, IR1, IR0) to decode

sixteen different possible instructions. Instructions are decoded as follows.

31 (MSB) 28 27 12 11 1 0(LSB)

Version (4 bits) Part number Manufacturer ID 1

0X0 (16-bit) (11-bit) 0X33

JTAG DEVICE IDENTIFICATION

INDUSTRIAL TEMPERATURE RANGE

IDT5T9821

EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER

The following sections provide a brief description of each instruction. For a

complete description refer to the IEEE Standard Test Access Port Specification

(IEEE Std. 1149.1-1990).

EXTEST

The required EXTEST instruction places the IC into an external boundary-

test mode and selects the boundary-scan register to be connected between

TDI and TDO. During this instruction, the boundary-scan register is accessed

to drive test data off-chip through the boundary outputs, and recieve test data

off-chip through the boundary inputs. As such, the EXTEST instruction is the

workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint

opens/shorts and of logic cluster function.

SAMPLE/PRELOAD

The required SAMPLE/PRELOAD instruction allows the IC to remain in a

normal functional mode and selects the boundary-scan register to be connected

between TDI and TDO. During this instruction, the boundary-scan register can

be accessed via a data scan operation, to take a sample of the functional data

entering and leaving the IC.

IDCODE

The optional IDCODE instruction allows the IC to remain in its functional mode

and selects the optional device identification register to be connected between

TDI and TDO. The device identification register is a 32-bit shift register

containing information regarding the IC manufacturer, device type, and

version code. Accessing the device identification register does not interfere

with the operation of the IC. Also, access to the device identification register

should be immediately available, via a TAP data-scan operation, after power-

up of the IC or after the TAP has been reset using the optional TRST pin or

by otherwise moving to the Test-Logic-Reset state.

PROGWRITE

The PROGWRITE instruction is for writing the IDT5T9821 configuration

data to the device’s volatile programming registers. This instruction selects the

programming register path for shifting data from TDI to TDO during data register

scanning. The programming register path has 112 registers (14 bytes)

between TDI and TDO. The 12 configuration data bytes are scanned in

through TDI first, starting with Bit 0. After scanning in the last configuration bit,

Bit 95, sixteen additional bits must be scanned in to place the configuration data

in the proper location. The last sixteen registers in the programming path are

reserved, read-only registers.

PROGREAD

The PROGREAD instruction is for reading out the IDT5T9821 configuration

data from the device’s volatile programming registers. This instruction selects

the programming register path for shifting data from TDI to TDO during data

TDI and TDO, and the first bit scanned out through TDO will be Bit 0 of the

configuration data.

PROGSAVE and PROGRESTORE (EEPROM OPERATION)

The PROGSAVE instruction is for copying the IDT5T9821 configuration

data from the device’s volatile programming registers to the EEPROM. This

instruction selects the BYPASS register path for shifting data from TDI to TDO

during data register scanning.

The PROGRESTORE instruction is for loading the IDT5T9821 configuration

data from the EEPROM to the device’s volatile programming registers. This

instruction selects the BYPASS register path for shifting data from TDI to TDO

during data register scanning.

During the execution of a PROGSAVE or PROGRESTORE instruction, the

IDT5T9821 will not accept a new programming instruction (read, write, save,

or restore). All non-programming JTAG instructions will function properly, but

the user should wait until the save or restore is complete before issuing a new

programming instruction. The time it takes for the save and restore instructions

to complete depends on the PLL oscillator frequency, F

VCO. The restore time,

TRESTORE, and the save time, TSAVE, can be calculated as follows:

TRESTORE

= 1.23X10

/FVCO

(mS)

SAVE

= 3.09X10

VCO

+ 52 (mS)

If a new programming instruction is issued before the save or restore

completes, the new instruction is ignored, and the BYPASS register path

remains in effect for shifting data from TDI to TDO during data register scanning.

In order for the ProgSave and ProgRestore instructions to function properly,

the IDT5T9821 must not be in power-down mode (PD must be HIGH), and

the PLL must be enabled (PLL_EN = LOW and Bit 57 = 0).

On power-up of the IDT5T9821, an automatic restore is performed to load

the EEPROM contents into the internal programming registers. The auto-

restore will not function properly if the device is in power-down mode (PD must

be HIGH). The device's auto-restore feature will function regardless of the state

of the PLL_EN pin or Bit 57. The time it takes for the device to complete the

auto-restore is approximately 3ms.

CLAMP

The optional CLAMP instruction loads the contents from the boundary-scan

be connected between TDI and TDO. During this instruction, data can be

shifted through the bypass register from TDI to TDO without affecting the

condition of the IC outputs.

HIGH-IMPEDANCE

The optional High-Impedance instruction sets all outputs (including two-state

as well as three-state types) of an IC to a disabled (high-impedance) state and

selects the one-bit bypass register to be connected between TDI and TDO.

During this instruction, data can be shifted through the bypass register from TDI

to TDO without affecting the condition of the IC outputs.

BYPASS

The required BYPASS instruction allows the IC to remain in a normal

functional mode and selects the one-bit bypass register to be connected

between TDI and TDO. The BYPASS instruction allows serial data to be

transferred through the IC from TDI to TDO without affecting the operation of

the IC.

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IDT5T9821NLI

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