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IDT5T9821NLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
7
INDUSTRIAL TEMPERATURE RANGE
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
JTAG/ I
2
C SERIAL DESCRIPTION, CONT.
Bit Description
20 Divide selection for bank 2
19 Divide selection for bank 3
18 Divide selection for bank 3
17 Divide selection for bank 3
16 Divide selection for bank 3
15 Divide selection for bank 3
14 Divide selection for bank 4
13 Divide selection for bank 4
12 Divide selection for bank 4
11 Divide selection for bank 4
10 Divide selection for bank 4
9 Divide selection for bank 5
8 Divide selection for bank 5
7 Divide selection for bank 5
6 Divide selection for bank 5
5 Divide selection for bank 5
4 Divide selection for FB bank
3 Divide selection for FB bank
2 Divide selection for FB bank
1 Divide selection for FB bank
0 Divide selection for FB bank
JTAG/ I
2
C SERIAL CONFIGURATIONS:
OUTPUT ENABLE/DISABLE
Bit 59 (OMODE) Bit 56-52 (nsOE) Output
X (X) 0 and (L) Normal Operation
0 and (L) 1 or (H) Tri-Sate
1 or (H) 1 or (H) Gated
(1)
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ and QFB are stopped in a HIGH/LOW state, while the
nQ and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its
corresponding Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I
2
C SERIAL CONFIGURATIONS:
POWERDOWN
PD Bit 59 (OMODE) Output
H X (X) Normal Operation
L 0 and (L) Tri-Sate
L 1 or (H) Gated
(1)
NOTE:
1. OMODE and its corresponding Bit 59 selects whether the outputs are gated LOW/
HIGH or tri-stated. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated. Bit 58 determines the level at which the outputs stop.
When Bit 58 is 0/ 1, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ
and QFB are stopped in a LOW/HIGH state. When OMODE is LOW and its
corresponding Bit 59 is 0, the outputs' disable state will be the tri-state.
JTAG/ I
2
C SERIAL CONFIGURATIONS:
CLOCK INPUT INTERFACE SELEC-
TION
(1)
Bit 31, 33, 35 Bit 30, 32, 34 Interface
0 0 Differential
(2)
0 1 2.5V LVTTL
1 1 1.8V LVTTL
NOTES:
1. All other states that are undefined in the table will be reserved.
2. Differential input interface for HSTL/eHSTL, LVEPECL (2.5V), and 2.5V/1.8V LVTTL.
JTAG/ I
2
C SERIAL CONFIGURATIONS:
OUTPUT DRIVE STRENGTH
SELECTION
(1)
Bit 37, 39, 41, Bit 36, 38, 40,
43, 45, 47 42, 44, 46 Interface
0 0 2.5V LVTTL
0 1 1.8V LVTTL
1 0 HSTL/eHSTL
NOTE:
1. All other states that are undefined in the table will be reserved.
8
INDUSTRIAL TEMPERATURE RANGE
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
JTAG/ I
2
C SERIAL CONFIGURATIONS: SKEW OR FREQUENCY SELECT
(1)
Bit 4, 9, 14, Bit 3, 8, 13, Bit 2, 7, 12, Bit 1, 6, 11, Bit 0, 5, 10, Output Skew
19, 24, 29 18, 23, 28 17, 22, 27 16, 21, 26 15, 20, 25
0 0 0 0 0 Zero Skew
1 0 0 0 0 Inverted
1 0 0 0 1 Divide-by-2
1 0 0 1 0 Divide-by-4
NOTE:
1. All other states that are undefined in the table will result in zero skew.
JTAG/ I
2
C SERIAL CONFIGURATIONS: FB DIVIDE-BY-N
(1)
Bit 51 Bit 50 Bit 49 Bit 48 Divide-by-N Permitted Output Divide-by-N connected to FB and FB/VREF2
(2)
0 0 0 0 1 1, 2, 4
0 0 0 1 2 1, 2
00103 1
0 0 1 1 4 1, 2
0 1 0 0 5 1, 2
0 1 0 1 6 1, 2
01108 1
011110 1
100012 1
NOTES:
1. All other states that are undefined in the table will be reserved.
2. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF [1:0]/VREF[1:0] inputs will be Fvco/N when the parts are
configured for frequency multiplication by using an undivided output for FB and FB/VREF2 and setting N (N = 1-6, 8, 10, 12).
EXTERNAL DIFFERENTIAL FEEDBACK
By providing a dedicated external differential feedback, the IDT5T9821
gives users flexibility with regard to divide selection. The FB and FB/
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0]
signals at the phase detector in order to drive the VCO. Phase differ-
ences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
INPUT/OUTPUT SELECTION
(1)
Input Output
(2)
2.5V LVTTL SE 2.5V LVTTL,
1.8V LVTTL SE 1.8V LVTTL,
2.5V LVTTL DSE HSTL,
1.8V LVTTL DSE eHSTL
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
NOTES:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations
of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require
the REF[1:0] /VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended
(DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2.
Differential (DIF) inputs are used only in differential mode.
2. For each output bank.
MASTER RESET FUNCTIONALITY
The IDT5T9821 performs a reset of the internal output divide circuitry
when all five output banks are disabled by toggling the nSOE pins
HIGH. When one or more banks of outputs are enabled by toggling the
nSOE LOW(if the corresponding nSOE programming bits are also set
LOW), the divide circuitry starts again from a known state. In the case
that the FB output is selected for divide-by-2 or divide-by-4, the FB
output will stop toggling while all five nSOE pins and bits are LOW, and
loss of lock will occur.
9
INDUSTRIAL TEMPERATURE RANGE
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
NOTE:
1. These inputs are normally wired to V
DD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,
the function and timing of the outputs may be glitched, and the PLL may require additional t
LOCK time before all datasheet limits are achieved.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Test Conditions Min. Max Unit
VIHH Input HIGH Voltage Level
(1)
3-Level Inputs Only VDD – 0.4 — V
VIMM Input MID Voltage Level
(1)
3-Level Inputs Only VDD/2 – 0.2 VDD/2 + 0.2 V
VILL Input LOW Voltage Level
(1)
3-Level Inputs Only — 0.4 V
V
IN = VDD HIGH Level — 200
I
3 3-Level Input DC Current VIN = VDD/2 MID Level –50 +50 µA
(ADDR0, ADDR1) VIN = GND LOW Level –200 —
I
PU Input Pull-Up Current VDD = Max., VIN = GND –100 — µA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL
(1)
Symbol Parameter Test Conditions Min. Typ.
(7)
Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V VI = VDDQN/GND — — ±5 µA
IIL Input LOW Current VDD = 2.7V VI = GND/VDDQN ——±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 +3.6 V
VDIF DC Differential Voltage
(2,8)
0.2 — V
VCM DC Common Mode Input Voltage
(3,8)
680 750 900 mV
VIH DC Input HIGH
(4,5,8)
VREF + 100 — mV
VIL DC Input LOW
(4,6,8)
—VREF - 100 mV
V
REF Single-Ended Reference Voltage
(4,8)
— 750 — mV
Output Characteristics
VOH Output HIGH Voltage IOH = -8mA VDDQN - 0.4 — V
IOH = -100µAVDDQN - 0.1 —
V
OL Output LOW Voltage IOL = 8mA — 0.4 V
IOL = 100µA — 0.1
V
OX nQ/nQ and FB/FB Output Crossing Point VDDQN/2 - 150 VDDQN/2 VDDQN/2 + 150 mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQN = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
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IDT5T9821NLI

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IC CLK DRIVER ZD PLL 68-VFQFPN
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