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INDUSTRIAL TEMPERATURE RANGE
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
I
2
C BUS DC CHARACTERISTICS
Symbol Parameter Conditions Min Typ Max Unit
VIH Input HIGH Level 0.7 * VDD V
VIL Input LOW Level 0.3 * VDD V
VHYS Hysteresis of Inputs 0.05 * VDD V
IIN Input Leakage Current ±1.0 µA
V
OL Output LOW Voltage IOL = 3 mA 0.4 V
I
2
C BUS AC CHARACTERISTICS FOR STANDARD MODE
Symbol Parameter Min Typ Max Unit
FSCLK Serial Clock Frequency (SCLK) 0 100 KHz
tBUF Bus free time between STOP and START 4.7 µs
tSU:START Setup Time, START 4.7 µs
tHD:START Hold Time, START 4 µs
tSU:DATA Setup Time, data input (SDA) 250 ns
tHD:DATA Hold Time, data input (SDA)
(1)
0 µs
tOVD Output data valid from clock 3.45 µs
CB Capacitive Load for Each Bus Line 400 pF
tR Rise Time, data and clock (SDA, SCLK) 1000 ns
tF Fall Time, data and clock (SDA, SCLK) 300 ns
tHIGH HIGH Time, clock (SCLK) 4 µs
tLOW LOW Time, clock (SCLK) 4.7 µs
t
SU:STOP Setup Time, STOP 4 µs
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2
C BUS AC CHARACTERISTICS FOR FAST MODE
Symbol Parameter Min Typ Max Unit
FSCLK Serial Clock Frequency (SCLK) 0 400 KHz
tBUF Bus free time between STOP and START 1.3 µs
tSU:START Setup Time, START 0.6 µs
tHD:START Hold Time, START 0.6 µs
tSU:DATA Setup Time, data input (SDA) 100 ns
tHD:DATA Hold Time, data input (SDA)
(1)
0 µs
tOVD Output data valid from clock 0.9 µs
CB Capacitive Load for Each Bus Line 400 pF
tR Rise Time, data and clock (SDA, SCLK) 20 + 0.1 * CB 300 ns
tF Fall Time, data and clock (SDA, SCLK) 20 + 0.1 * CB 300 ns
tHIGH HIGH Time, clock (SCLK) 0.6 µs
tLOW LOW Time, clock (SCLK) 1.3 µs
t
SU:STOP Setup Time, STOP 0.6 µs
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of
SCLK.
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of
SCLK.
