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INDUSTRIAL TEMPERATURE RANGE
IDT5T9821
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER
JTAG
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter Min. Max. Units
tTCLK JTAG Clock Input Period 100 — ns
tTCLKHIGH JTAG Clock HIGH 40 — ns
tTCLKLOW JTAG Clock Low 40 — ns
tTCLKRISE JTAG Clock Rise Time — 5
(1)
ns
tTCLKFALL JTAG Clock Fall Time — 5
(1)
ns
tRST JTAG Reset 50 — ns
tRSR JTAG Reset Recovery 50 — ns
NOTE:
1. Guaranteed by design.
Standard JTAG Timing
NOTE:
t1 = tTCLKLOW
t2 = tTCLKHIGH
t3 = tTCLKFALL
t4 = tTCLKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
TCLK
TDI/TMS
TDO
TRST
t
TCLK
t1
t2
t3
t4
t5
t6
t
DS tDH
tDO
TDO
SYSTEM INTERFACE PARAMETERS
Symbol Parameter Min. Max. Units
tDO Data Output
(1)
—20ns
tDOH Data Output Hold
(1)
0—ns
tDS Data Input, tRISE = 3ns 10 — ns
tDH Data Input, tFALL = 3ns 10 — ns
NOTE:
1. 50pF loading on external output signals.
PROGRAMMING NOTES
Once the IDT5T9821 has been programmed either with a ProgWrite or ProgRestore instruction, the device will attempt to achieve phase lock using the new
PLL configuration. If there is a valif REF and FB input clock connected to the device, and it does not achieve lock, the user should issue a ProgRead instruction
to confirm that the PLL configuration data is valid.
On power-up and before the automatic ProgRestore instruction has completed, the internal programming registers will contain the value of '0' for all bits 95:0.
The PLL will remain at the minimum frequency and will not achieve phase lock until after the automatic restore is completed. If the outputs are enabled by the
nSOE pins, the outputs will toggle at the minimum frequency. If the outputs are disabled by the nSOE pins, and the OMODE pin is set high, the nQ[1:0] and
QFB are stopped HIGH, while QFB is stopped LOW.
