Data Sheet ADV202
Rev. D | Page 13 of 40
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter Description Min Typ Max Unit
DREQ
PULSE
DREQ
Pulse Width
1
1 15 JCLK
2
cycles
t
DREQ
RTN
WE
to
DREQ
Deassert (DR × Pulse = 0) 2.5 3.5 × JCLK + 7.5 ns JCLK cycles
t
DACK
SU
DACK
to
WE
Setup 0 ns
t
SU
Data Setup 2.5 ns
t
Data Hold 2 ns
WE
LO
WE
Assert Pulse Width 1.5 JCLK cycles
WE
HI
WE
Deassert Pulse Width 1.5 JCLK cycles
t
DREQ
WAIT
Last Burst Access to Next
DREQ
2.5 4.5 × JCLK + 7.5 ns
3
JCLK cycles
1
Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a value that is not 0. Pulse width depends on the value programmed.
2
For a definition of JCLK, see the PLL section.
3
If sufficient space is available in FIFO.
04723-022
DREQ
DACK
WE
HDATA
WE
HI
WE
LO
t
DACKSU
t
HD
t
SU
0 1 13 14 15
t
DREQWAIT
DREQ
PULSE
Figure 13. Burst Write Cycle for
DREQ
/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] NOT Programmed to a Value of 0000)
04723-023
DREQ
DACK
WE
HDATA
WE
HI
WE
LO
t
DACKSU
t
HD
t
SU
0 1 13 14 15
t
DREQWAIT
t
DREQRTN
Figure 14. Burst Write Cycle for
DREQ
/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
