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ADV202BBCZ-150

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
Data Sheet ADV202
Rev. D | Page 3 of 40
REVISION HISTORY
1/12—Rev. C to Rev. D
Updated Outline Dimensions ........................................................ 39
Changes to Ordering Guide ........................................................... 40
11/06—Rev. B to Rev. C
Deleted ANC FIFO References ........................................ Universal
Changes to Features .......................................................................... 1
Changes to Figure 1........................................................................... 1
Changes to JPEG2000 Feature Support Section ............................ 4
Changes to Figure 8......................................................................... 10
Changes to Figure 10 ...................................................................... 11
Changes to Figure 12 ...................................................................... 12
Changes to External DMA Mode—FIFO Write,
Burst Mode Section ......................................................................... 13
Changes to External DMA Mode—FIFO Read,
Burst Mode Section ......................................................................... 13
Changes to Table 11 ........................................................................ 17
Changes to Figure 22 ...................................................................... 18
Deleted SPI Port Timing Section .................................................. 18
Added Absolute Maximum Ratings Section ............................... 19
Changes to Pin BGA Assignments and Function
Descriptions Section ....................................................................... 20
Changes to ADV202 Interface Section ........................................ 27
Changes to Table 19 ........................................................................ 29
Changes to Indirect Registers Section .......................................... 30
Changes to PLL Section.................................................................. 31
Changes to Table 23 ........................................................................ 31
Changes to Video Input Formats Section .................................... 32
Changes to Figure 24 ...................................................................... 34
Changes to Figure 26 ...................................................................... 35
Changes to Ordering Guide ........................................................... 40
1/05—Rev. A to Rev. B
Updated Outline Dimensions........................................................ 39
12/04—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Table 2 ............................................................................ 4
Changes to Table 16 ........................................................................ 24
Changes to Table 23 ........................................................................ 32
7/04—Revision 0: Initial Version
ADV202 Data Sheet
Rev. D | Page 4 of 40
GENERAL DESCRIPTION
(continued from Page 1)
The ADV202 can process images at a rate of 40 MSPS in
reversible mode and at higher rates when used in irreversible
mode. The ADV202 contains a dedicated wavelet transform
engine, three entropy codecs, an on-board memory system, and
an embedded RISC processor that can provide a complete
JPEG2000 compression/decompression solution.
The wavelet processor supports the 9/7 irreversible wavelet
transform and the 5/3 wavelet transform in reversible and
irreversible modes. The entropy codecs support all features in
the JPEG2000 Part 1 specification, except Maxshift ROI.
The ADV202 operates on a rectangular array of pixel samples
called a tile. A tile can contain a complete image, up to the
maximum supported size, or some portion of an image. The
maximum horizontal tile size supported depends on the wavelet
transform selected and the number of samples in the tile.
Images larger than the ADV202’s maximum tile size can be
broken into individual tiles and then sent sequentially to the
chip while still maintaining a single, fully compliant JPEG2000
code stream for the entire image.
JPEG2000 FEATURE SUPPORT
The ADV202 supports a broad set of features that are included
in Part 1 of the JPEG2000 standard (ISO/IEC 15444). See
Getting Started with ADV202 for information on the JPEG2000
features that the ADV202 currently supports.
Depending on the particular application requirements, the
ADV202 can provide varying levels of JPEG2000 compression
support. It can provide raw code-block and attribute data
output, which allow the host software to have complete control
over the generation of the JPEG2000 code stream and other
aspects of the compression process such as bit-rate control.
Otherwise, the ADV202 can create a complete, fully compliant
JPEG2000 code stream (.j2c) and enhanced file formats such as
.jp2 and .j2c. See Getting Started with ADV202 for information
on the formats that the ADV202 currently supports.
Application notes and other ADV202 support documents can
be accessed over the ADV202 product page at:
• http://www.analog.com/ADV202Notes or from
• ftp://ftp.analog.com/pub/Digital_Imaging/ADV202_FTP_s
ite_contents_3.html
Data Sheet ADV202
Rev. D | Page 5 of 40
SPECIFICATIONS
SUPPLY VOLTAGES AND CURRENT
Table 1.
Parameter Description Min Typ Max Unit
VDD DC Supply Voltage, Core 1.425 1.5 1.575 V
IOVDD DC Supply Voltage, I/O 2.375 3.3 3.63 V
PLLVDD DC Supply Voltage, PLL 1.425 1.5 1.575 V
V
INPUT
Input Range −0.3 V
DDI/O
+ 0.3 V
Temp Operating Ambient Temperature Range in Free Air −40 +25 +85 °C
I
DD
Static Current
1
300 mA
Dynamic Current, Core (JCLK Frequency = 150 MHz)
2
570 mA
Dynamic Current, Core (JCLK Frequency = 108 MHz) 420 mA
Dynamic Current, Core (JCLK Frequency = 81 MHz) 325 mA
Dynamic Current, I/O 20 mA
Dynamic Current, PLL 2.6 mA
1
No clock or I/O activity.
2
ADV202-150 only.
INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter Description Test Conditions Min Typ Max Unit
V
IH (3.3 V)
High Level Input Voltage VDD = max 2.2 V
V
IH (2.5 V)
High Level Input Voltage VDD = max 1.9 V
V
IL (3.3 V, 2.5 V)
Low Level Input Voltage VDD = min 0.6 V
V
OH (3.3 V )
High Level Output Voltage VDD = min, I
OH
= −0.5 mA 2.4 V
V
OH (2.5 V )
High Level Output Voltage VDD = min, I
OH
= −0.5 mA 2.0 V
V
OL (3.3 V, 2.5 V)
Low Level Output Voltage VDD = min, I
OL
= 2 mA 0.4 V
I
IH
High Level Input Current VDD = max, V
IN
= VDD 1.0 µA
I
IL
Low Level Input Current VDD = max, V
IN
= 0 V 1 µA
I
OZH
High Level Three-State Leakage Current VDD = max, V
IN
= VDD 1.0 µA
I
OZL
Low Level Three-State Leakage Current VDD = max, V
IN
= 0 V 1.0 µA
C
I
Input Pin Capacitance 8 pF
C
O
Output Pin Capacitance 8 pF
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ADV202BBCZ-150

Mfr. #:
Buy ADV202BBCZ-150
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs JPEG 2000 Video IC 150 MHz
Lifecycle:
New from this manufacturer.
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