Data Sheet ADV202
Rev. D | Page 27 of 40
ADV202 INTERFACE
There are several possible modes to interface to the ADV202 using
the VDATA bus and the HDATA bus or the HDATA bus alone.
VIDEO INTERFACE (VDATA BUS)
The video interface can be used in applications in which
uncompressed pixel data is on a separate bus from compressed
data. For example, it is possible to use the VDATA bus to input
uncompressed video while using the HDATA bus to output the
compressed data. This interface is ideal for applications
requiring very high throughput such as live video capture.
Optionally, the ADV202 can compress ITU.R-BT656 resolution
video on a field-by-field basis or on a two-fields-combined
basis, which yields significantly more efficient compression
performance. Additionally, high definition digital video such as
SMPTE274M (1080i) is supported using two or more ADV202
devices.
The video interface can support video data or still image data
input/output, 8-, 10-, and 12-bit single or multiplexed
components. The VDATA interface supports digital video in
YCbCr format or single component format. YCbCr data must
be in 4:2:2 format.
Video data can be input/output in several different modes on
the VDATA bus, as described in Table 18. In all these modes,
the pixel clock must be input on the VCLK pin.
Table 18. Video Input/Output Modes
Mode Description
EAV/SAV Accepts video with embedded EAV/SAV codes, where
the YCbCr data is interleaved onto a single bus.
HVF Accepts video data accompanied with separate H, V,
and F signals where YCbCr data is interleaved onto a
single bus.
Raw
Video
Used for still picture data and nonstandard video.
VFRM, VSTRB, and VRDY are used to program the
dimensions of the image.
HOST INTERFACE (HDATA BUS)
The ADV202 can connect directly to a wide variety of host
processors and ASICs using an asynchronous SRAM-style
interface, DMA accesses, or streaming mode (JDATA) interface.
The ADV202 supports 16- and 32-bit buses for control and
8-, 16-, and 32-bit buses for data transfer.
The control and data channel bus widths can be specified
independently, which allows the ADV202 to support applica-
tions that require control and data buses of different widths.
The host interface is used for configuration, control, and status
functions, as well as for transferring compressed data streams. It
can be used for uncompressed data transfers in certain modes.
The host interface can be shared by as many as four concurrent
data streams in addition to control and status communications.
The data streams are
• Uncompressed tile data (for example, still image data)
• Fully encoded JPEG2000 code stream (or unpackaged code
blocks)
• Code-block attributes
The ADV202 uses big endian byte alignment for 16- and 32-bit
transfers. All data is left-justified (MSB).
Pixel Input on the Host Interface
Pixel input on the host interface supports 8-, 10-, 12-, 14-, and
16-bit raw pixel data formats. It can be used for pixel (still
image) input/output or compressed video output. Because there
are no timing codes or sync signals associated with the input
data on the host interface, dimension registers and internal
counters are used and must be programmed to indicate the start
and end of the frame. See the technical note on using HIPI
mode for details on how to use the ADV202 in this mode.
Host Bus Configuration
For maximum flexibility, the host interface provides several
configurations to meet particular system requirements. The
default bus mode uses the same pins to transfer control, status,
and data to and from the ADV202. In this mode, the ADV202
can support 16- and 32-bit control transfers and 8-, 16-, and
32-bit data transfers. The size of these buses can be selected
independently, allowing, for example, a 16-bit microcontroller
to configure and control the ADV202 while still providing
32-bit data transfers to an ASIC or external memory system.
DIRECT AND INDIRECT REGISTERS
To minimize pin count and cost, the number of address pins has
been limited to four, which yields a total direct address space of
16 locations. These locations are most commonly used by the
external controller and are, therefore, accessible directly. All
other registers in the ADV202 can be accessed indirectly
through the IADDR and IDATA registers.
CONTROL ACCESS REGISTERS
With the exception of the indirect address and data registers
(IADDR and IDATA), all control/status registers in the ADV202
are 16 bits wide and are half-word (16-bit) addressable only.
When 32-bit host mode is enabled, the upper 16 bits of the
HDATA bus are ignored on writes and return all 0s on reads of
16-bit registers.
