ADV202BBCZ-150 Datasheet ADV202BBCZRL-150, ADV202BBCZ-135, ADV202BBCZ-150 | P16-P18

Data Sheet ADV202

Rev. D | Page 15 of 40

04723-026

DREQ

DACK

HDATA

DACKSU

0 1 13 14 15

DREQWAIT

DREQRTN

Figure 17. Burst Read Cycle for

DREQ

DACK

DMA Mode for Assigned DMA Channel

(EMOD0/EDMOD1[14:11] Programmed to a Value of 0000)

04723-027

DREQ

DACK

RDFB

HDATA

DACKSU

0 1 13 14 15

DREQWAIT

DREQRTN

Figure 18. Burst Read Cycle, Fly-By DMA Mode

(

DREQ

Pulse Width Is Programmable)

ADV202 Data Sheet

Rev. D | Page 16 of 40

STREAMING MODE (JDATA)—FIFO READ/WRITE

Table 10.

Parameter Description Min Typ Max Unit

JDATA

MCLK to JDATA Valid 1.5 2.5 × JCLK + 7.0 ns JCLK cycles

VALID

MCLK to VALID Assert/Deassert 1.5 2.5 × JCLK + .7.0 ns JCLK cycles

HOLD

HOLD Setup to Rising MCLK 3 ns

HOLD

HOLD Hold from Rising MCLK 3 ns

JDATA

JDATA Setup to Rising MCLK 3 ns

JDATA

JDATA Hold from Rising MCLK 3 ns

For a definition of JCLK, see the PLL section.

04723-028

MCLK

JDATA

VALID

HOLD

VALID

JDATA

Figure 19. Streaming Mode Timing—Encode Mode JDATA Output

04723-029

MCLK

JDATA

VALID

HOLD

VALID

JDATA

Figure 20. Streaming Mode Timing—Decode Mode JDATA Input

Data Sheet ADV202

Rev. D | Page 17 of 40

VDATA MODE TIMING

Table 11.

Parameter Description Min Typ Max Unit

VDATA

VCLK to VDATA Valid Delay (VDATA Output) 12 ns

VDATA

VDATA Setup to Rising VCLK (VDATA Input) 4 ns

VDATA

VDATA Hold from Rising VCLK (VDATA Input) 4 ns

HSYNC

HSYNC Setup to Rising VCLK 3 ns

HSYNC

HSYNC Hold from Rising VCLK 4 ns

HSYNC

VCLK to HSYNC Valid Delay 12 ns

VSYNC

VSYNC Setup to Rising VCLK 3 ns

VSYNC

VSYNC Hold from Rising VCLK 4 ns

VSYNC

VCLK to VSYNC Valid Delay 12 ns

FIELD

FIELD Setup to Rising VCLK 4 ns

FIELD

FIELD Hold from Rising VCLK 3 ns

FIELD

VCLK to FIELD Valid 12 ns

SYNC DELAY Decode Data Sync Delay for HD Input with EAV/SAV Codes 7 VCLK cycles

Decode Data Sync Delay for SD Input with EAV/SAV Codes 9 VCLK cycles

Decode Data Sync Delay for HVF Input (from First Rising VCLK after HSYNC Low to

First Data Sample)

10 VCLK cycles

04723-030

Cr Y

Cb Y FF

EAV

FF SAV

Cb Y

VDATA

VCLK

VDATA(IN)

ENCODE CCIR-656 LINE

VDATA

VCLK

VDATA(OUT)

Cr Y Cb Y

FF EAV

FF SAV

Cb Y

DECODE MASTER CCIR-656 LINE

VCLK

VDATA(OUT)

VDATA

SYNC DELAY

CrY Y

Cb Y FF EAV

FF SAV

Cb Y

*HSYNC AND VSYNC DO NOT HAVE TO BE APPLIED SIMULTANEOUSLY

VCLK

VDATA(IN)

HSYNC

VSYNC

CrY Y Cb

Y Cr Y Cb Y

YCrYCb

HSYNC

ENCODE HVF MODE

DECODE SLAVE CCIR-656 LINE

HSYNC

VSYNC

Cb Y Cr Y Cb

CbY

VCLK

HSYNC

VSYNC

DECODE SLAVE HVF MODE

HSYNC

VDATA

SYNC DELAY

VSYNC

Cb Y Cr Y

Figure 21. Video Mode Timing

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P41

ADV202BBCZ-150

Mfr. #:

Buy ADV202BBCZ-150

Manufacturer:

Analog Devices Inc.

Description:

Interface - CODECs JPEG 2000 Video IC 150 MHz

Lifecycle:

New from this manufacturer.

Delivery:

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ADV202BBCZ-150

ADV202BBCZ-150

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