ZL30409 Data Sheet
3
Zarlink Semiconductor Inc.
Pin Description
Pin # Name Description
1,10,
23,31
GND Ground. 0 Volts.
2RST
Reset (Input). A logic low at this input resets the ZL30409. To ensure proper operation, the
device must be reset after reference signal frequency changes and power-up. The RST pin
should be held low for a minimum of 300 ns. While the RST pin is low, all frame pulses except
RSP and TSP and all clock outputs except C6o, C16o and C19o are at logic high. The RSP,
TSP, C6o, C16o are at logic low during reset. The C19o is free-running during reset. Following
a reset, the input reference source and output clocks and frame pulses are phase aligned as
shown in Figure 13.
3TCLR
TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase as shown in
Figure 13. The TCLR
pin should be held low for a minimum of 300 ns. This pin is internally
pulled down to GND.
4ICInternal Connection. Leave unconnected.
5 SEC Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies (8 kHz, 1.544 MHz,
2.048 MHz or 19.44 MHz) may be used. The selection of the input reference is based upon
the MS1, MS2, RSEL, and PCCi control inputs.This pin is internally pulled up to V
DD
.
6PRIPrimary Reference (Input). See SEC pin description. This pin is internally pulled up to V
DD
.
7,17
28,35
V
DD
Positive Supply Voltage. +3.3V
DC
nominal.
8OSCoOscillator Master Clock (CMOS Output). For crystal operation, a 20 MHz crystal is
connected from this pin to OSCi, see Figure 9. Not suitable for driving other devices. For clock
oscillator operation, this pin is left unconnected, see Figure 8.
9OSCiOscillator Master Clock (CMOS Input). For crystal operation, a 20 MHz crystal is
connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is
connected to a clock source, see Figure 8.
11 F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8 kHz 61ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mb/s. See Figure 14.
12 F0o
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 14.
13 RSP Receive Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
14 TSP Transmit Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
15 F8o Frame Pulse (CMOS Output). This is an 8 kHz 122 ns active high framing pulse, which
marks the beginning of a frame. See Figure 14.
16 C1.5o Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.
