ZL30409 Data Sheet
13
Zarlink Semiconductor Inc.
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has
settled to a steady state.
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
initial input to output phase difference
initial input to output frequency difference
synchronizer loop filter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. See AC Electrical Characteristics - Performance for Maximum Phase Lock TIme.
ZL30409 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference
within approximately 500 ms.
ZL30409 and Network Specifications
The ZL30409 meets applicable PLL requirements (intrinsic jitter/wander, jitter/wander tolerance, jitter/wander
transfer, frequency accuracy, frequency holdover accuracy, capture range and MTIE during reference
rearrangement) for the following specifications.
1. Telcordia GR-1244-CORE for Stratum 4
2. AT&T TR62411 (DS1) December 1990 for Stratum 4
3. ANSI T1.101 (DS1) February 1994 for Stratum 4
4. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
MTIE S() TIEmax t() TIEmin t()=
ZL30409 Data Sheet
14
Zarlink Semiconductor Inc.
Figure 7 - Control State Diagram
Description State
Input Controls Freerun
Normal
(PRI)
Normal
(SEC)
Holdover
(PRI)
Holdover
(SEC)
MS2 MS1 RSEL PCCi S0 S1 S2 S1H S2H
0 0 0 0 S1 - S1 MTIE S1 S1 MTIE
0 0 0 1 S1 - S1 MTIE S1 MTIE S1 MTIE
0 0 1 X S2 S2 MTIE - S2 MTIE S2 MTIE
01 0 X / S1H / - /
01 1 X / S2H S2H / -
10 X X - S0 S0 S0 S0
Legend:
- No Change
/ Not Valid
MTIE State change occurs with TIE Corrector Circuit
Refer to Control State Diagram for state changes to and from Auto-Holdover State
Table 4 - Control State Table
Phase Re-Alignment
Phase Continuity Maintained (without TIE Corrector Circuit)
Phase Continuity Maintained (with TIE Corrector Circuit)
NOTES:
(XXX) MS2 MS1 RSEL
{A} Invalid Reference Signal
Movement to Normal State from any
state requires a valid input signal
{A} {A}
S0
Freerun
(10X)
S2H
Holdover
Secondary
(011)
S1H
Holdover
Primary
(010)
S2
Normal
Secondary
(001)
S1
Normal
Primary
(000)
(PCCi=0)
(PCCi=1)
S1A
Auto-Holdover
Primary
(000)
S2A
Auto-Holdover
Secondary
(001)
ZL30409 Data Sheet
15
Zarlink Semiconductor Inc.
Applications
This section contains ZL30409 application specific details for clock and crystal operation, reset operation, power
supply decoupling, and control operation.
Master Clock
The ZL30409 can use either a clock or crystal as the master timing source.
In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source
at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source
may be ±100 ppm. For applications requiring an accurate Freerun Mode, such as AT&T TR62411, the tolerance of
the master timing source must be no greater than
±32 ppm.
Another consideration in determining the accuracy of the master timing source is the desired capture range. The
sum of the accuracy of the master timing source and the capture range of the ZL30409 will always equal 230 ppm.
For example, if the master timing source is 100 ppm, then the capture range will be 130 ppm.
Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. This includes
absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
Figure 8 - Clock Oscillator Circuit
For applications requiring
±32 ppm clock accuracy, the following clock oscillator module may be used.
FOX F7C-2E3-20.0MHz
Frequency: 20 MHz
Tolerance: 25 ppm 0C to 70C
Rise & Fall Time: 10 ns (0.33 V 2.97 V 15 pF)
Duty Cycle: 40% to 60%
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30409, and the OSCo
output should be left open as shown in Figure 8.
Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a
crystal, resistor and capacitors is shown in Figure 9.
+3.3V
20MHz OUT
GND 0.1uF
+3.3V
OSCo
ZL30409
OSCi
No Connection

ZL30409DDF1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Phase Locked Loops - PLL Pb Free T1/E1 SYS.SYNC+STRATUM 3 H/OVER
Lifecycle:
New from this manufacturer.
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