ZL30409 Data Sheet
7
Zarlink Semiconductor Inc.
Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the
feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Loop Filter. The Frequency Select MUX allows the
proper feedback signal to be selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) from generated output
clocks.
Figure 4 - DPLL Block Diagram
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). This filter ensures that the jitter
transfer requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the filtered signal from the Loop Filter, and based on its
value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on
the state of the ZL30409.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30 ms to 60 ms) frequency the
DCO was generating while in Normal Mode.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - When the ZL30409 acquires frequency lock (frequency lock means the center frequency of the PLL
is identical to the line frequency), then the lock signal changes from low to high. For specific Lock Indicator design
recommendations see the Applications - Lock Indicator section.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to generate clocks shown in Figure 5. The
Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit, and a
DS2 Divider Circuit to generate the required output signals. These four tapped delay lines are designed to generate
16.384 MHz, 12.352 MHz, 12.624 MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.384 MHz signal to generate four clock outputs (C2, C4
, C8, C16) and five frame
pulse outputs (F0o
, F8o, F16o, RSP, TSP). The C8o, C4o and C2o clocks are generated by simply dividing the
C16o
clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384 MHz signal to generate the C1.5o clock by dividing the internal C12 clock
by eight. This output has a nominal 50% duty cycle.
Control
Circuit
State Select
from
Input Impairment Monitor
State Select
from
State Machine
Feedback Signal
from
Frequency Select MUX
DPLL Reference
to
Output Interface Circuit
Virtual Reference
from
TIE Corrector
Loop Filter
Digitally
Controlled
Oscillator
Phase
Detector
