ZL30409DDF1 Datasheet ZL30409DDF1, ZL30409DDE1 | P10-P12

ZL30409 Data Sheet

Zarlink Semiconductor Inc.

From a reset condition, the ZL30409 will take up to 30 seconds (see AC Electrical Characteristics) of input

reference signal to output signals which are synchronized (phase locked) to the reference input.

The selection of input references is control dependent as shown in state Table 4. The reference frequencies are

selected by the frequency control pins FS2 and FS1 as shown in Table 1.

Fast Lock Mode

Fast Lock Mode is a submode of Normal Mode, it is used to allow the ZL30409 to lock to a reference more quickly

than Normal Mode will allow. Typically, the PLL will lock to the incoming reference within 500 ms if the FLOCK pin is

set high.

Holdover Mode

Holdover Mode is typically used for short durations (e.g., 2 seconds) while network synchronization is temporarily

disrupted.

In Holdover Mode, the ZL30409 provides timing and synchronization signals, which are not locked to an external

reference signal, but are based on storage techniques. The storage value is determined while the device is in

Normal Mode and locked to an external reference signal.

When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the ZL30409

output reference frequency is stored alternately in two memory locations every 30 ms. When the device is switched

into Holdover Mode, the value in memory from between 30 ms and 60 ms is used to set the output frequency of the

device.

The frequency accuracy of Holdover Mode is

±0.05ppm, which translates to a worst case 35 frame (125 us) slips in

24 hours. This satisfies the AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3 requirement of

±0.37ppm

(255 frame slips per 24 hours).

Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock while in Holdover Mode, drift on

the Master Clock directly affects the Holdover Mode accuracy. Note that the absolute Master Clock (OSCi)

accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a

±32 ppm master clock may have a temperature coefficient of ±0.1 ppm per degree C. So a ±10 degree change in

temperature, while the ZL30409 is in Holdover Mode may result in an additional offset (over the

±0.05 ppm) in

frequency accuracy of

±1 ppm. Which is much greater than the ±0.05 ppm of the ZL30409.

The other factor affecting accuracy is large jitter on the reference input prior (30 ms to 60 ms) to the mode switch.

For instance, jitter of 7.5UI at 700 Hz may reduce the Holdover Mode accuracy from

±0.05 ppm to ±0.10 ppm.

Freerun Mode

Freerun Mode is typically used when a master clock source is required, or immediately following system power-up

before network synchronization is achieved.

In Freerun Mode, the ZL30409 provides timing and synchronization signals which are based on the master clock

frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).

The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a

±32 ppm output clock

is required, the master clock must also be

±32 ppm. See Applications - Crystal and Clock Oscillator sections.

ZL30409 Data Sheet

Zarlink Semiconductor Inc.

ZL30409 Measures of Performance

The following are some synchronizer performance indicators and their corresponding definitions.

Intrinsic Jitter

Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by

applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may

also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring

the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the

applicable standards. In the ZL30409, the intrinsic Jitter is limited to less than 0.02UI on the 2.048 MHz and

1.544 MHz clocks.

Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the

presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied

jitter magnitude and jitter frequency depends on the applicable standards.

Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter

at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured

with various filters depending on the applicable standards. The ZL30409 jitter transfer is determined by the Loop

Filter corner frequency (1.9 Hz).

The ZL30409 has twelve outputs with three possible input frequencies (except for 19.44 MHz, which is internally

divided to 8 KHz) for a total of 36 possible jitter transfer functions. Since all outputs are derived from the same

signal, the jitter transfer values for the four cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to

2.048 MHz can be applied to all outputs.

It should be noted that 1UI at 1.544 MHz is 644 ns, which is not equal to 1UI at 2.048 MHz, which is 488 ns.

Consequently, a transfer value using different input and output frequencies must be calculated in common units

(e.g., seconds) as shown in the following example.

What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is

18 dB?

Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on

the three jitter transfer functions provided.

Note that the resulting jitter transfer functions for all combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz and

19.44 MHz) and outputs (8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz) for a

given input signal (jitter frequency and jitter amplitude) are the same.

OutputT1 InputT1

A–

-------





×10=

OutputT1 20

18–

---------





×10 2.5UI T1()==

OutputE1 OutputT1

644ns()

488ns()

-------------------

3.3UI T1()=×=

OutputE1 OutputT1

1UIT1()

1UIE1()

----------------------

×=

ZL30409 Data Sheet

Zarlink Semiconductor Inc.

Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for

large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter

signals (e.g., 75% of the specified maximum jitter tolerance).

Frequency Accuracy

Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an

external reference, but is operating in a free running mode. For the ZL30409, the Freerun accuracy is equal to the

Master Clock (OSCi) accuracy.

Holdover Accuracy

Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external

reference signal, but is operating using storage techniques. For the ZL30409, the storage value is determined while

the device is in Normal Mode and locked to an external reference signal.

The absolute Master Clock (OSCi) accuracy of the ZL30409 does not affect Holdover accuracy, but the change in

OSCi accuracy while in Holdover Mode does.

Capture Range

Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull

into synchronization. The ZL30409 capture range is equal to

±230 ppm minus the accuracy of the master clock

(OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm.

If there are no clock transitions at the active reference pin, the ZL30409 will automatically go to Holdover Mode and

indicate this condition with the Holdover pin.

Lock Range

This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock

range is equal to the capture range for the ZL30409.

Time Interval Error (TIE)

TIE is the time delay between a given timing signal and an ideal timing signal.

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ZL30409DDF1

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Manufacturer:

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Description:

Phase Locked Loops - PLL Pb Free T1/E1 SYS.SYNC+STRATUM 3 H/OVER

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