ZL30409 Data Sheet
16
Zarlink Semiconductor Inc.
Figure 9 - Crystal Oscillator Circuit
The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance.
Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance
contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances, and stray
capacitances have a major effect on the accuracy of the oscillator frequency.
The trimmer capacitor shown in Figure 9 may be used to compensate for capacitive effects. If accuracy is not a
concern, then the trimmer may be removed, the 39 pF capacitor may be increased to 56 pF, and a wider tolerance
crystal may be substituted.
The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler
oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal
specification is as follows.
Frequency: 20 MHz
Tolerance: As required
Oscillation Mode: Fundamental
Resonance Mode: Parallel
Load Capacitance: 32 pF
Maximum Series Resistance: 35
Approximate Drive Level: 1 mW
e.g., R1B23B32-20.0MHz
(20 ppm absolute,
±6 ppm 0C to 50C, 32 pF, 25 )
TIE Correction (using PCCi)
When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will
prevent unwanted accumulated phase change between the input and output.
For instance, 10 Normal to Holdover to Normal mode change sequences occur, and in each case Holdover was
entered for 2 s. Each mode change sequence could account for a phase change as large as 350 ns. Thus, the
accumulated phase change could be as large as 3.5 us, and, the overall MTIE could be as large as 3.5 us.
OSCo
56pF
1M
39pF
3-50pF
20MHz
ZL30409
OSCi
100
1uH
1uH inductor: may improve stability and is optional
Phase
hold
0.05ppm 2s× 100ns==
Phase
state
50ns 200ns 250ns=+=
Phase
10
10 250ns 100ns+()× 3.5us==
ZL30409 Data Sheet
17
Zarlink Semiconductor Inc.
0.05 ppm is the accuracy of Holdover Mode
50 ns is the maximum phase continuity of the ZL30409 from Normal Mode to Holdover Mode
200 ns is the maximum phase continuity of the ZL30409 from Holdover Mode to Normal Mode (with or
without TIE Corrector Circuit)
When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case
holdover was entered for 2 s, each mode change sequence could still account for a phase change as large as
350 ns. However, there would be no accumulated phase change, since the input to output phase is re-aligned after
every Holdover to Normal state change. The overall MTIE would only be 350 ns.
Reset Circuit
A simple power up reset circuit with about a 50 us reset low time is shown in Figure 10. Resistor R
P
is for protection
only and limits current into the RST
pin during power down conditions. The reset low time is not critical but should
be greater than 300 ns.
Figure 10 - Power-Up Reset Circuit
+3.3V
RST
R
P
1k
C
10nF
R
10k
ZL30409
ZL30409 Data Sheet
18
Zarlink Semiconductor Inc.
Lock Indicator
The LOCK pin toggles at a random rate when the PLL is frequency locked to the input reference. In Figure 11 the
RC-time-constant circuit can be used to hold the high state of the LOCK pin.
Once the PLL is frequency locked to the input reference, the minimum duration of LOCK pin’s high state would be
32 ms and the maximum duration of LOCK pin’s low state would not exceed 1 second. The following equations can
be used to calculate the charge and discharge times of the capacitor.
t
C
= - R
D
C ln(1 – V
T+
/V
DD
) = 240 µs
t
C
= Capacitor’s charge time
R
D
= Dynamic resistance of the diode (100 )
C = Capacitor value (1 µF)
V
T+
= Positive going threshold voltage of the
Schmidt Trigger (3.0 V)
V
DD
= 3.3 V
t
D
= - R C ln(V
T-
/V
DD
) = 1.65 seconds
t
D
= Capacitor’s discharge time
R = Resistor value (3.3 M)
C = Capacitor value (1 µF)
V
T-
= Negative going threshold voltage of the
Schmidt Trigger (2.0 V)
V
DD
= 3.3 V
Figure 11 - Time-constant Circuit
A digital alternative to the RC-time-constant circuit is presented in Figure 12. The circuit in Figure 12 can be used to
generate a steady lock signal. The circuit monitors the ZL30409’s LOCK pin, as long as it detects a positive pulse
every 1.024 seconds or less, the Advanced Lock output will remain high. If no positive pulse is detected on the
LOCK output within 1.024 seconds, the Advanced LOCK output will go low.
R=3.3 M
IN4148
LOCK
74HC14 74HC14
C=1 µf
+
LOCK
ZL30409

ZL30409DDF1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Phase Locked Loops - PLL Pb Free T1/E1 SYS.SYNC+STRATUM 3 H/OVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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