ZL30409DDF1 Datasheet ZL30409DDF1, ZL30409DDE1 | P4-P6

ZL30409 Data Sheet

Zarlink Semiconductor Inc.

18 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to

the input reference.

19 C2o Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s.

20 C4o

Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s

and 4.096 Mb/s.

21 C19o Clock 19.44 MHz (CMOS Output). This output is used in OC3/STS3 applications.

22 FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference

(less than 500 ms locking time).

24 IC Internal Connection. Tie low for normal operation.

25 C8o Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at 8.192 Mb/s.

26 C16o

Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a

16.384 MHz clock.

27 C6o Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.

29 HOLD

OVER

Holdover (CMOS Output). This output goes to a logic high whenever the PLL goes into

holdover mode.

30 PCCi Phase Continuity Control Input (Input). The signal at this pin affects the state changes

between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and

Secondary Normal Mode. See State Machine control section for details. The logic level at this

input is gated in by the rising edge of F8o.

32 NC No connection. Leave unconnected

33,34 IC Internal Connection. Connect to GND.

36 MS2 Mode/Control Select 2 (Input). This input determines the state (Normal, Holdover or

Freerun) of operation. See Table 3 for details. The logic level at this input is gated in by the

rising edge of F8o

37 MS1 Mode/Control Select 1 (Input). See MS2 pin description. The logic level at this input is gated

in by the rising edge of F8o. This pin is internally pulled down to GND.

38 RSEL Reference Source Select (Input). A logic low selects the PRI (primary) reference source as

the input reference signal and a logic high selects the SEC (secondary) input. The logic level

at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled

down to GND.

39 IC Internal Connection. Connect to GND.

40 FS2 Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four

possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the PRI

and SEC inputs. See Table 1.

41 FS1 Frequency Select 1 (Input). See pin description for FS2.

42 IC Internal Connection. Connect to GND.

43 IC Internal Connection. Leave unconnected.

44 TDO Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling

edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.

Pin Description (continued)

Pin # Name Description

ZL30409 Data Sheet

Zarlink Semiconductor Inc.

Functional Description

The ZL30409 is a System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface

circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which is

described in the following sections.

Reference Select MUX Circuit

The ZL30409 accepts two simultaneous reference input signals and operates on their falling edges. Either the

primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE

Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1

and Table 4.

Frequency Select MUX Circuit

The ZL30409 operates with one of four possible input reference frequencies (8 kHz, 1.544 MHz, 2.048 MHz or

19.44 MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at

the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST

)

must be performed after every frequency select input change. See Table 1.

Table 1 - Input Frequency Selection

Time Interval Error (TIE) Corrector Circuit

The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or

SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.

During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary

reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL

would lead to unacceptable phase changes in the output signal.

45 TDI Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin.

This pin is internally pulled up to V

46 TRST

Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the

Test-Logic-Reset state. If not used, this pin should be held low.

47 TCK Test Clock (Input): Provides the clock to the JTAG test logic. This pin is internally pulled up to

48 TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP

controller. This pin is internally pulled up to V

FS2 FS1 Input Frequency

0 0 19.44 MHz

01 8kHz

1 0 1.544 MHz

1 1 2.048 MHz

Pin Description (continued)

Pin # Name Description

ZL30409 Data Sheet

Zarlink Semiconductor Inc.

Figure 3 - TIE Corrector Circuit

As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the

signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is

input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.

During a switch from one reference to the other, the State Machine first changes the mode of the device

from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an

accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the

current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the

Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as

the previous reference signal would have been if the reference switch not taken place. The State Machine then

returns the device to Normal Mode.

The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,

no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change

at the input of the DPLL, or at the output of the DPLL.

Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual

reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.

This phase error is a function of the difference in phase between the two input reference signals during reference

rearrangements. Each time a reference switch is made, the delay between input signal and output signal will

change. The value of this delay is the accumulation of the error measured during each reference switch.

The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR

) pin. A

minimum reset pulse width is 300 ns. This results in a phase alignment between the input reference signal and the

output signal as shown in Figure 14.

Digital Phase Lock Loop (DPLL)

As shown in Figure 4, the DPLL of the ZL30409 consists of a Phase Detector, Loop Filter, Digitally Controlled

Oscillator, and a Control Circuit.

Programmable

Delay Circuit

Control Signal

Delay Value

TCLR

Resets Delay

Compare

Circuit

TIE Corrector

Enable

from

State Machine

Control

Circuit

Feedback

Signal from

Frequency

Select MUX

PRI or SEC

from

Reference

Select Mux

Virtual

Reference

to DPLL

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ZL30409DDF1

Mfr. #:

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Manufacturer:

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Description:

Phase Locked Loops - PLL Pb Free T1/E1 SYS.SYNC+STRATUM 3 H/OVER

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