OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LTC4066EUF#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LTC4066/LTC4066-1
22
4066fc
APPLICATIONS INFORMATION
Any time a battery is connected to the BAT pin and the
SHDN pin is low, the BAT pin current can be monitored
with the following equation:
I
V
R
BAT
ISTAT
ISTAT
= • 1000
where |I
BAT
| is the absolute value of the BAT pin current,
V
ISTAT
is the voltage on the I
STAT
pin and R
ISTAT
is the total
resistance from the I
STAT
pin to ground.
The POL pin has two states: high impedance and strong
pull-down. High impedance indicates that current is fl ow-
ing from BAT to OUT (ideal diode function) and strong
pull-down indicates that current is fl owing from OUT to
BAT (charging). If an external ADC is used to convert the
I
STAT
voltage, then the POL pin can be thought of as a
sign bit.
When the ideal diode function is operating, the I
STAT
pin
cannot monitor ideal diode load currents less than about
1mA. For any ideal diode load current less than 1mA, the
I
STAT
pin will source a constant current of approximately
1μA. However, when the battery charger function is operat-
ing, the I
STAT
pin will continue to source one-thousandth
of the battery charge current even if the charge current
drops to less than 1mA.
When choosing the value of R
ISTAT
, two details must be
considered. For the battery charger function, the value of
R
ISTAT
programs the charge current below which the CHRG
pin transitions to its high impedance state (see CHRG
Status Output Pin). Furthermore, the available common
mode range on the I
STAT
pin needed to maintain an accurate
ratio between I
BAT
and I
ISTAT
is limited. When charging, the
I
STAT
pin voltage should not exceed approximately V
OUT
– 0.5V. When the ideal diode is functioning, the I
STAT
pin
voltage should not exceed approximately V
BAT
– 0.5V (for
the typical minimum operating voltage for the ideal diode
this value would be 2.8V – 0.5V = 2.3V). Typically, it is this
second case that is the limiting situation since V
BAT
is typi-
cally lower than V
OUT
(while charging) and transient ideal
diode loads tend to be greater than typical charge currents
(causing a higher voltage on the I
STAT
pin). Therefore,
choosing a value of R
ISTAT
based on the CHRG detection
current may limit the maximum ideal diode load current
that can be sensed accurately. Consider an example:
a) Desired charge current = 850mA
b) Desired CHRG detection current = 100mA
c) Maximum transient ideal diode current = 1.5A
Calculate:
a) R
PROG
= (1V/850mA) • 50,000 = 59k
b) R
ISTAT
= 100V/100mA = 1k
c) V
ISTAT(MAX)
= 1.5A/1000 • 1k = 1.5V
In this example, there is no common mode problem because
the maximum I
STAT
voltage (1.5V) is well below the 2.3V
minimum. However, if, instead of 100mA, the desired CHRG
detection current was lowered to 40mA, then the desired
R
ISTAT
resistor would increase to 2.5k (100V/40mA) and
the maximum I
STAT
voltage would increase to 3.75V (as-
suming no change in the 1.5A maximum ideal diode cur-
rent). Therefore, ideal diode currents greater than 920mA
(2.3V/2.5k • 1000) might not be reported accurately. To
calculate the maximum ideal diode current that will be
reported accurately:
I
VV
R
DMON MAX
BAT
ISTAT
()
–.
=
05
LTC4066/LTC4066-1
23
4066fc
APPLICATIONS INFORMATION
Current Limit Undervoltage Lockout
An internal undervoltage lockout circuit monitors the
input voltage and disables the input current limit circuits
until V
IN
rises above the undervoltage lockout threshold.
The current limit UVLO circuit has a built-in hysteresis of
125mV. Furthermore, to protect against reverse current in
the power MOSFET, the current limit UVLO circuit disables
the current limit (i.e., forces the input power path to a high
impedance state) if V
OUT
exceeds V
IN
. If the current limit
UVLO comparator is tripped, the current limit circuits will
not come out of shutdown until V
OUT
falls 50mV below
the V
IN
voltage.
Charger Undervoltage Lockout
An internal undervoltage lockout circuit monitors the V
OUT
voltage and disables the battery charger circuits until
V
OUT
rises above the undervoltage lockout threshold. The
battery charger UVLO circuit has a built-in hysteresis of
125mV. Furthermore, to protect against reverse current
in the power MOSFET, the charger UVLO circuit keeps the
charger shutdown if V
BAT
exceeds V
OUT
. If the charger UVLO
comparator is tripped, the charger circuits will not come
out of shutdown until V
OUT
exceeds V
BAT
by 50mV.
Shutdown
The LTC4066/LTC4066-1 can be shutdown by forcing the
SHDN pin greater than 1.2V. In shutdown, the currents
drawn from IN, OUT and BAT are decreased to less than
2.5μA and the internal battery charge timer and end-of-
charge comparator output are reset. All power paths are
put in a high impedance state.
Suspend
The LTC4066/LTC4066-1 can be put in suspend mode by
forcing the SUSP pin greater than 1.2V. In suspend mode
the ideal diode function from BAT to OUT is kept alive.
If power is applied to the OUT pin externally (i.e., a wall
adapter is present) then charging will be unaffected. Current
drawn from the IN pin is reduced to 50μA. Suspend mode
is intended to comply with the USB Power Specifi cation
mode of the same name.
Selecting WALL Input Resistors
The WALL input pin identifi es the presence of a wall adapter.
This information is used to disconnect the input pin, IN,
from the OUT pin in order to prevent back conduction to
whatever may be connected to the input. It also forces the
ACPR pin low when the voltage at the WALL pin exceeds
the input threshold. The WALL pin has a 1.225V rising
threshold and approximately 30mV of hysteresis.
The wall adapter detection threshold is set by the follow-
ing equation:
V Adapter V
R
R
V Adapter V
R
R
TH WALL
HYST WALL HYST
() •
() •
()
=+
⎛
⎝
⎜
⎞
⎠
⎟
=+
⎛
⎝
⎜
⎞
⎠
⎟
1
1
2
1
1
2
where V
TH
(Adapter) is the wall adapter detection threshold,
V
WALL
is the WALL pin rising threshold (typically 1.225V),
R1 is the resistor from the wall adapter input to WALL and
R2 is the resistor from WALL to GND.
LTC4066/LTC4066-1
24
4066fc
APPLICATIONS INFORMATION
Consider an example where the V
TH
(Adapter) is to be set
somewhere around 4.5V. Resistance on the WALL pin
should be kept relatively low (~10k) in order to prevent
false tripping of the wall comparator due to leakages as-
sociated with the switching element used to connect the
adapter to OUT. Pick R2 to be 10k and solve for R1:
RR
V Adapter
V
Rk
V
V
kk
TH
WALL
12 1
110
45
1 225
1 10 2 67 26 7
=
⎛
⎝
⎜
⎞
⎠
⎟
=
⎛
⎝
⎜
⎞
⎠
⎟
==
•
()
–
•
.
.
–•..
The nearest 1% resistor is 26.7k. Therefore, R1 = 26.7k
and the rising trip point should be 4.50V.
V Adapter mV
k
k
mV
HYST
() •
.
.≈+
⎛
⎝
⎜
⎞
⎠
⎟
≈30 1
26 7
10
110 1
The hysteresis is going to be approximately 110mV for
this example.
Power Dissipation
The conditions that cause the LTC4066/LTC4066-1 to
reduce charge current due to the thermal protection
feedback can be approximated by considering the power
dissipated in the part. For high charge currents and a wall
adapter applied to V
OUT
, the LTC4066/LTC4066-1 power
dissipation is approximately:
P
D
= (V
OUT
– V
BAT
) • I
BAT
where P
D
is the power dissipated, V
OUT
is the supply
voltage, V
BAT
is the battery voltage and I
BAT
is the battery
charge current. It is not necessary to perform any worst-
case power dissipation scenarios because the LTC4066/
LTC4066-1 will automatically reduce the charge current
to maintain the die temperature at approximately 105°C.
However, the approximate ambient temperature at which
the thermal feedback begins to protect the IC is:
T
A
= 105°C – P
D
• θ
JA
T
A
= 105°C – (V
OUT
– V
BAT
) • I
BAT
• θ
JA
Example: Consider an LTC4066/LTC4066-1 operating from
a wall adapter with 5V at V
OUT
providing 0.8A to a 3V
Li-Ion battery. The ambient temperature above which the
LTC4066/LTC4066-1 will begin to reduce the 0.8A charge
current, is approximately:
T
A
= 105°C – (5V – 3V) • 0.8A • 37°C/W
T
A
= 105°C – 1.6W • 37°C/W = 105°C – 59°C = 46°C
The LTC4066/LTC4066-1 can be used above 46°C, but the
charge current will be reduced below 0.8A. The charge
current at a given ambient temperature can be approxi-
mated by:
I
CT
VV
BAT
A
OUT BAT JA
=
°
()
105 –
–•θ
Consider the above example with an ambient tem-
perature of 55°C. The charge current will be reduced to
approximately:
I
CC
VV CW
C
CA
A
BAT
=
°°
()
°
=
°
°
=
105 55
53 37
50
74
0 675
–
–• / /
.
Board Layout Considerations
In order to be able to deliver maximum charge current
under all conditions, it is critical that the Exposed Pad
on the backside of the LTC4066/LTC4066-1 package is
soldered to the board. Correctly soldered to a 2500mm
2
double-sided 1oz. copper board, the LTC4066/LTC4066-1
has a thermal resistance of approximately 37°C/W. Failure
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

LTC4066EUF#PBF

Mfr. #:
Buy LTC4066EUF#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management USB Power Manager and Li-Ion Charger
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet