1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2010, Zarlink Semiconductor Inc. All Rights Reserved.
Zarlink has introduced a new generation family of
AEC (ZL38002 and ZL38004). Zarlink recommends
these products for new designs.
Features
Contains two echo cancellers: 112 ms acoustic
echo canceller + 16 ms line echo canceller
Works with low cost voice codec. ITU-T G.711 or
signed mag /A-Law, or linear 2’s comp
Each port may operate in different format
Advanced NLP design - full duplex speech with
no switched loss on audio paths
Fast re-convergence time: tracks changing echo
environment quickly
Adaptation algorithm converges even during
Double-Talk
Designed for exceptional performance in high
background noise environments
Provides protection against narrow-band signal
divergence
Howling prevention stops uncontrolled oscillation
in high loop gain conditions
Offset nulling of all PCM channels
Serial micro-controller interface
ST-BUS, GCI, or variable-rate SSI PCM interfaces
User gain control provided for speaker path
(-24dB to +48dB in 3dB steps)
18 dB gain at Sout to compensate for high ERL
environments
AGC on speaker path
Handles up to 0 dB acoustic echo return loss
Transparent data transfer and mute options
20 MHz master clock operation
Low power mode during PCM Bypass
Bootloadable for future factory software upgrades
2.7 V to 3.6 V supply voltage; 5 V tolerant inputs
September 2010
Ordering Information
ZL38001QDG1 48 Pin TQFP* Trays, Bake & Drypack
ZL38001DGF1 36 Pin SSOP* Tape & Reel,
Bake & Drypack
ZL38001DGE1 36 Pin SSOP* Tubes, Bake & Drypack
*Pb Free Matte Tin
-40C to +85C
ZL38001
AEC for Analog Hands-Free
Communication
Data Sheet
Figure 1 - Functional Block Diagram
Rout
MD1
MD2
PORT 2
Sin
Line ECho Path
S
1
Micro
Interface
Program
RAM
Program
ROM
FORMAT
Linear/
/A-Law
Offset
Null
Linear
/A-Law/
Linear/
/A-Law
Adaptive
Filter
Offset
Null
VDD
VSS
RESET
F0i
BCLK/C4i
MCLK
Sout
Rin
DATA1
DATA2
CS
SCLK
ENA2
LAW
AGC
User
Gain
+
-
ADV
+
-
-24 -> +21 dB
R
1
R
2
R
3
S
2
S
3
NLP
ADV
NLP
Linear
/A-Law/
+
+
Howling
Controller
PORT 1
NBSD
Adaptive
Filter
UNIT
CONTROL
Detector
Talk
Double
NBSD
ENA1
Limiter
Limiter
ACOUSTIC ECHO PATH
18dB
Gain
ZL38001 Data Sheet
2
Zarlink Semiconductor Inc.
Applications
Hands-free in automobile applications
MT93L16 ZL38001 ZL38002 ZL38003
Description AEC for analog hands-
free communication
AEC for analog hands-
free communication
AEC with noise reduction for digital
hands-free communication
AEC with noise reduction & codecs
for digital hands-free communication
Application Analog Desktop phone
Analog Intercom
Analog Desktop phone
Analog Intercom
Hands-free Car Kits
Digital Desktop Phone Home Security
Intercom & Pedestals
Hands-free Car Kits
Digital Desktop Phone Home Security
Intercom & Pedestals
Features
AEC 1 channel 1 channel 1 channel 1 channel
LEC 1 channel 1 channel Custom Load Custom Load
Gains User Gain User Gain/18 dB
Gain on Sout
User Gain + System tuning gains User Gain + System tuning gains
Noise
Reduction
NN Y Y
Integrated
Codecs
N N N dual channel
Table 1 - Acoustic Echo Cancellation Family
ZL38001 Data Sheet
3
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
SSOP
Pin #
TQFP
Pin #
Name Description
143ENA1SSI Enable Strobe/ST-BUS & GCI Mode for Rin/Sout (Input). This pin
has dual functions depending on whether SSI or ST-BUS/GCI is selected.
For SSI, this strobe must be present for frame synchronization. This is an
active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for on Rin/Sout pins. Strobe period is 125
microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1
pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI
Operation description).
245MD1ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI
operation, this pin, in conjunction with the ENA1 pin, will select the proper
mode for Rin/Sout pins (see ST-BUS and GCI Operation description).
Connect this pin to Vss in SSI mode.
346ENA2SSI Enable Strobe /ST-BUS & GCI Mode for Sin/Rout (Input). This pin
has dual functions depending on whether SSI or ST-BUS/GCI is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide,
enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125
microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin,
selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation
description).
447MD2ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI
operation, this pin in conjunction with the ENA2 pin, selects the proper
mode for Sin/Rout pins (see ST-BUS and GCI Operation description).
Connect this pin to Vss in SSI mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
19
20
28
27
26
25
24
23
22
21
DATA2
VDD
NC
IC
NC
DATA1
SCLK
Sout
Rout
BCLK/C4i
IC
IC
Sin
Rin
IC
MD2
MD1
F0i
FORMAT
IC
LAW
ENA1
RESET
NC
ENA2
MCLK
CS
32
31
VSS
NC
30
29
VSS2
VDD2
IC
17
18
33
34
35
36
MCLK2
IC
IC
IC
TQFP
3436
38
40
42
44
46
48
16
14
12108642
CS
RESETB
NC
NC
Sout
DATA2
SCLK
Sin
IC
IC
NC
IC
IC
NC
LAW
MCLK2
ENA2
IC
IC
IC
NC
NC
IC
NC
18
20
22
24
263032 28
MD2
MD1
ENA1
NC
NC
NC
BCLK/C4i
VSS
VDD2
FORMAT
F0i
Rout
VSS2
NC
MCLK
NC
IC
NC
NC
DATA1
NC
VDD
NC
Rin
SSOP

ZL38001DGF1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Communication ICs - Various Pb Free ACOUSTIC ECHO CANC.+LOW ERL COMP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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