ZL38001 Data Sheet
25
Zarlink Semiconductor Inc.
Timing is over recommended temperature and power supply voltages.
AC Electrical Characteristics
- Serial Data Interfaces - Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics Sym. Min. Typ. Max. Units Test Notes
1 MCLK Frequency f
CLK
19.15 20.5 MHz
2 BCLK/C4i
Clock High t
BCH,
t
C4H
90 ns
3 BCLK/C4i
Clock Low t
BLL,
t
C4L
90 ns
4 BCLK/C4i
Period t
BCP
240 7900 ns
5 SSI Enable Strobe to Data Delay (first
bit)
t
SD
80 ns C
L
= 150 pF
6 SSI Data Output Delay (excluding
first bit)
t
DD
80 ns C
L
= 150 pF
7 SSI Output Active to High Impedance t
AHZ
80 ns C
L
= 150 pF
8 SSI Enable Strobe Signal Setup t
SSS
10 t
BCP
-15
ns
9 SSI Enable Strobe Signal Hold t
SSH
15 t
BCP
-10
ns
10 SSI Data Input Setup t
DIS
10 ns
11 SSI Data Input Hold t
DIH
15 ns
12 ST-BUS/GCI F0i
Setup t
F0iS
20 150 ns
13 ST-BUS/GCI F0i
Hold t
F0iH
20 150 ns
14 ST-BUS/GCI Data Output delay t
DSD
80 ns C
L
= 150 pF
15 ST-BUS/GCI Output Active to High
Impedance
t
ASHZ
80 ns C
L
= 150 pF
16 ST-BUS/GCI Data Input Hold time t
DSH
20 ns
17 ST-BUS/GCI Data Input Setup time t
DSS
20 ns
ZL38001 Data Sheet
26
Zarlink Semiconductor Inc.
Timing is over recommended temperature range and recommended power supply voltages.
Figure 10 - Master Clock - MCLK
AC Electrical Characteristics
- Microport Timing
Characteristics Sym. Min. Typ. Max. Units Test Notes
1 Input Data Setup t
IDS
30 ns
2 Input Data Hold t
IDH
30 ns
3 Output Data Delay t
ODD
100 ns C
L
= 150 pF
4 Serial Clock Period t
SCP
500 ns
5 SCLK Pulse Width High t
SCH
250 ns
6 SCLK Pulse Width Low t
SCL
250 ns
7 CS Setup-Intel t
CSSI
200 ns
8CS
Setup-Motorola t
CSSM
100 ns
9CS
Hold t
CSH
100 ns
10 CS
to Output High Impedance t
OHZ
100 ns C
L
= 150 pF
Characteristic Symbol CMOS Level Units
CMOS reference level V
CT
0.5*V
DD
V
Input HIGH level V
H
0.9*V
DD
V
Input LOW level V
L
0.1*V
DD
V
Rise/Fall HIGH measurement point V
HM
0.7*V
DD
V
Rise/Fall LOW measurement point V
LM
0.3*V
DD
V
Table 7 - Reference Level Definition for Timing Measurements
MCLK
(I)
V
H
V
L
V
CT
T=1/f
CLK
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
(see Table 8 for symbol definitions)
ZL38001 Data Sheet
27
Zarlink Semiconductor Inc.
Figure 11 - GCI Data Port Timing
Figure 12 - ST-BUS Data Port Timing
Sout/Rout
(O)
V
CT
C4i
(I)
V
H
V
L
V
CT
F0i
(I)
V
H
V
L
V
CT
Rin/Sin
(I)
V
H
V
L
V
CT
t
F0iS
t
F0iH
t
DSS
t
DSH
t
DSD
t
ASHZ
t
C4H
t
C4L
Bit 6
Bit 7
Bit 6
start of frame
input sampled
Bit 7
Sout/Rout
(O)
V
CT
C4i
(I)
V
H
V
L
V
CT
F0i
(I)
V
H
V
L
V
CT
Rin/Sin
(I)
V
H
V
L
V
CT
t
F0iS
t
F0iH
t
DSS
t
DSH
t
DSD
t
ASHZ
t
C4H
t
C4L
Bit 7 Bit 6
Bit 6
start of frame
input sampled
Bit 7

ZL38001DGF1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Communication ICs - Various Pb Free ACOUSTIC ECHO CANC.+LOW ERL COMP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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