ZL38001 Data Sheet
39
Zarlink Semiconductor Inc.
Register Table 15 - Receive (Rout) Peak Detect Register 2 (ROPD2)
Register Table 16 - Send (Sin) Peak Detect Register 1 (SIPD1)
Bit Name Description
7ROPD
15
These peak detector registers allow the user to monitor the receive out signal
(Rout) peak level at reference point R3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
6ROPD
14
5ROPD
13
4ROPD
12
3ROPD
11
2ROPD
10
1ROPD
9
0ROPD
8
Bit Name Description
7SIPD
7
These peak detector registers allow the user to monitor the receive in signal
(Sin) peak level at reference point S1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
6SIPD
6
5SIPD
5
4SIPD
4
3SIPD
3
2SIPD
2
1SIPD
1
0SIPD
0
External Read Address: 3B
H
Reset Value: 00
H
76543210
ROPD
15
ROPD
14
ROPD
13
ROPD
12
ROPD
11
ROPD
10
ROPD
9
ROPD
8
External Read Address: 36
H
Reset Value: 00
H
76543210
SIPD
7
SIPD
6
SIPD
5
SIPD
4
SIPD
3
SIPD
2
SIPD
1
SIPD
0
