ZL38001 Data Sheet
43
Zarlink Semiconductor Inc.
Register Table 23 - Rout Limiter Register 2 (RL2)
Register Table 24 - Sout Limiter Register (SL)
Bit Name Description
7L
8
In conjunction with bit 7 (L
0
) of the above (RL1) register, this register (RL2)
allows the user to program the output Limiter threshold value in the Rout path.
Default value is (07D)h which is equal to 3.14 dBmo
Maximum value is (1FF)h = 15 dBmo
Minimum value is (001)h = -38 dBmo
6L
7
5L
6
4L
5
3L
4
2L
3
1L
2
0L
1
Bit Name Description
7L
4
This register allows the user to program the output Limiter threshold value in
the Rout path.
Default value is (1D)h which is equal to 3.14 dBmo
Maximum value is (1F)h
6L
3
5L
2
4L
1
3L
0
2 - RESERVED. Must be keep as 1.
1 - RESERVED. Must be keep as 0.
0 - RESERVED. Must be keep as 1.
External Read Address: 25
H
Reset Value: 3E
H
76543210
L
8
L
7
L
6
L
5
L
4
L
3
L
2
L
1
External Read Address: 26
H
Reset Value: 3D
H
76543210
L
4
L
3
L
2
L
1
L
0
