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ZL38001DGF1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
ZL38001 Data Sheet
34
Zarlink Semiconductor Inc.
Register Table 6 - Receive Gain Control Register
Bit Name Description
7 Reserved Must keep as Logic 0.
6 Reserved Must keep as Logic 1.
5 Reserved Must keep as Logic 1.
4-0 G4-0 User Gain Control on the Rin/Rout path (Tolerance of gains: +/- 0.15 dB).
The hexadecimal number represents G3 to G0 value in the table below.
External Read/Write Address:20
H
Reset Value: 6D
H
76543210
-
- - G4 G3 G2 G1 G0
Register Value Gain Register Value Gain
0h -24 dB 10h +24 dB
1h -21 dB 11h +27 dB
2h -18 dB 12h +30 dB
3h -15 dB 13h +33 dB
4h -12 dB 14h +36 dB
5h -9 dB 15h +39 dB
6h -6 dB 16h +42 dB
7h -3 dB 17h +45 dB
8h 0dB 18h +48dB
9h +3 dB 19h Reserved
Ah +6 dB 1Ah Reserved
Bh +9 dB 1Bh Reserved
Ch +12 dB 1Ch Reserved
Dh +15 dB 1Dh Reserved
Eh +18 dB 1Eh Reserved
Fh +21 dB 1Fh Reserved
ZL38001 Data Sheet
35
Zarlink Semiconductor Inc.
Register Table 7 - Double Talk Gain Control Register 1 (DTGCR1)
Register Table 8 - Double Talk Gain Control Register 2 (DTGCR2)
Bit Name Description
7 - RESERVED. Must keep as 0.
6 - RESERVED. Must keep as 0.
5 - RESERVED. Must keep as 1.
4 DTRGain This bit controls the gain level at Rout during double talk. When this bit is high
12 dB of attenuation is injected into the Rout path during double talk. When
this bit is low the gain pad is disabled.
3 - RESERVED. Must keep as 0.
2 - RESERVED. Must keep as 1.
1 - RESERVED. Must keep as 0.
0 - RESERVED. Must keep as 1.
Bit Name Description
7 - RESERVED. Must keep as 0.
6 - RESERVED. Must keep as 0.
5 - RESERVED. Must keep as 0.
4 DTSGain This bit controls the gain level at Sout during double talk. When this bit is high
12 dB of attenuation is injected into the Sout path during double talk. When
this bit is low the gain pad is disabled.
3 - RESERVED. Must keep as 0.
2 - RESERVED. Must keep as 0.
1 - RESERVED. Must keep as 0.
0 - RESERVED. Must keep as 0.
External Read/Write Address: 32
H
Reset Value: 25
H
76543210
HG
2
HG
1
HG
0
DTGain----
External Read/Write Address: 12
H
Reset Value: 00
H
76543210
---DTSGain --
ZL38001 Data Sheet
36
Zarlink Semiconductor Inc.
Register Table 9 - Double Talk detection Threshold Register (DTDT)
Register Table 10 - Receive (Rin) Peak Detect Register 1 (RIPD1)
Bit Name Description
7DTDT
2
6DTDT
1
5DTDT
0
4 - RESERVED. Must keep as 0.
3 - RESERVED. Must keep as 0.
2 - RESERVED. Must keep as 0.
1 - RESERVED. Must keep as 0.
0 - RESERVED. Must keep as 1.
Bit Name Description
7RIPD
7
These peak detector registers allow the user to monitor the receive in signal
(Rin) peak level at reference point R1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
6RIPD
6
5RIPD
5
4RIPD
4
3RIPD
3
2RIPD
2
1RIPD
1
0RIPD
0
External Read/Write Address: 31
H
Reset Value: 21
H
76543210
DTDT
2
DTDT
1
DTDT
0
-----
DTDT
2,
DTDT
1,
DTDT
0
Value DTDT DTDT
2,
DTDT
1,
DTDT
0
Value DTDT
000 -12 dB 100 +12 dB
001 -6dB 101 +18dB
010 0 dB 110 +24 dB
011 +6dB 111 +30dB
External Read Address: 16
H
Reset Value: 00
H
76543210
RIPD
7
RIPD
6
RIPD
5
RIPD
4
RIPD
3
RIPD
2
RIPD
1
RIPD
0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

ZL38001DGF1

Mfr. #:
Buy ZL38001DGF1
Manufacturer:
Microchip / Microsemi
Description:
Communication ICs - Various Pb Free ACOUSTIC ECHO CANC.+LOW ERL COMP
Lifecycle:
New from this manufacturer.
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