ZL38001 Data Sheet
4
Zarlink Semiconductor Inc.
548RinReceive PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM
input stream. Data may be in either companded or 2’s complement linear
format. This is the Receive Input channel from the line (or network) side.
Data bits are clocked in following SSI, GCI or ST-BUS timing requirements.
62SinSend PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input
stream. Data may be in either companded or 2’s complement linear format.
This is the Send Input channel (from the microphone). Data bits are
clocked in following SSI, GCI or ST-BUS timing requirements.
73ICInternal Connection (Input). Must be tied to Vss.
85MCLKMaster Clock (Input). Nominal 20 MHz Master Clock input (may be
asynchronous relative to 8 KHz frame signal.) Tie together with MCLK2
(pin 33).
9,10,11 6, 7, 8 IC Internal Connection (Input). Must be tied to Vss.
12 9 LAW A/
Law Select (Input). When low, selects Law companded PCM.
When high, selects A-Law companded PCM. This control is for both serial
pcm ports.
13 11 FORMAT ITU-T/Sign Mag
(Input). When low, selects sign-magnitude PCM code.
When high, selects ITU-T (G.711) PCM code. This control is for both serial
pcm ports.
14 13 RESET
Reset / Power-down (Input). An active low resets the device and puts the
ZL38001 into a low-power stand-by mode.
17 16 SCLK Serial Port Synchronous Clock (Input). Data clock for the serial
microport interface.
18 17 CS
Serial Port Chip Select (Input). Enables serial microport interface data
transfers. Active low.
19 19 DATA2 Serial Data Receive (Input). In Motorola/National serial microport
operation, the DATA2 pin is used for receiving data. In Intel serial microport
operation, the DATA2 pin is not used and must be tied to Vss or Vdd.
20 21 DATA1 Serial Data Port (Bidirectional). In Motorola/National serial microport
operation, the DATA1 pin is used for transmitting data. In Intel serial
microport operation, the DATA1 pin is used for transmitting and receiving
data.
22 23 VDD Positive Power Supply (Input). Nominally 3.3 volts.
23 24 Sout Send PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM
output stream. Data may be in either companded or 2’s complement linear
PCM format. This is the Send Out signal after acoustic echo cancellation
and non-linear processing. Data bits are clocked out following SSI, ST-
BUS or GCI timing requirements.
24 26 Rout Receive PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM
output stream. Data may be in either companded or 2’s complement linear
PCM format. This is the Receive out signal after line echo cancellation non-
linear processing, AGC and gain control. Data bits are clocked out
following SSI, ST-BUS or GCI timing requirements.
Pin Description (continued)
SSOP
Pin #
TQFP
Pin #
Name Description
ZL38001 Data Sheet
5
Zarlink Semiconductor Inc.
25 27 F0i Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low
(or active-high) frame alignment pulse, respectively. SSI operation is
enabled by connecting this pin to Vss.
26 29 BCLK/C4i
Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz
to 4.096 MHz bit clock. This clock must be synchronous with ENA1 and
ENA2 enable strobes.
In ST-BUS or GCI operation, C4i
pin must be connected to the 4.096 MHz
(C4
) system clock.
27, 28 30, 31 IC Internal Connection (Input). Tie to Vss.
29 33 VSS2 Digital Ground (Input). Nominally 0 volts.
30 34 VDD2 Positive Power Supply (Input). Nominally 3.3 volts (tie together with
VDD, pin 22).
31 35 VSS Digital Ground (Input). Nominally 0 volts (tie together with VSS2, pin 29).
33 38 MCLK2 Master Clock (Input). Nominal 20 MHz master clock (tie together with
MCLK, pin 8).
34,35,36
39, 40, 41 IC Internal Connection (Input). Tie to Vss.
15, 16, 21,
32
1, 4, 10, 12,
14, 15, 18,
20, 22, 25,
28, 32, 36,
37, 42, 44
NC No Connect (Output). This pin should be left unconnected.
Pin Description (continued)
SSOP
Pin #
TQFP
Pin #
Name Description
ZL38001 Data Sheet
Table of Contents
6
Zarlink Semiconductor Inc.
1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Adaptation Speed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Advanced Non-Linear Processor (ADV-NLP)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Howling Detector (HWLD)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Offset Null Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7 User Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 AGC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.9 18 dB Gain Pad at Sout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.10 Mute Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.11 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.12 Adaptation Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.13 ZL38001 Throughput Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.14 Power Down / Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 PCM Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 ST-BUS and GCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 SSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 PCM Law and Format Control (LAW, FORMAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Linear PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Bit Clock (BCLK/C4i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Master Clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.0 Microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Bootload Process and Execution from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.0 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

ZL38001DGF1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Communication ICs - Various Pb Free ACOUSTIC ECHO CANC.+LOW ERL COMP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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