JANUARY 25, 2017 13 VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
5P35021 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5P35021. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Recommended Operating Conditions
Item Rating
Supply Voltage, VDDA, VDD33, VDDSE,VDDDIFF 3.465V
Supply Voltage, VBAT 3.465V
Inputs
XIN/CLKIN 0V to 3.3V voltage swing for both LVCMOS or DIFF CLK
Other inputs -0.5V to VDD33/VDDSEx
Outputs, VDDSEx (LVCMOS) -0.5V to VDDSEx/VDDDIFF+ 0.5V
Outputs, IO (SDA) 10mA
Package Thermal Impedance, ΘJA 42°C/W (0 mps)
Package Thermal Impedance, ΘJC 41.8°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
ESD Human Body Model, 2500V
ESD Charge Device Model, 1000V
Junction Temperature 125°C
Symbol Parameter Min Typ Max Unit
Power supply voltage for supporting 1.8V outputs
1.71 1.8 1.89 V
Power supply voltage for supporting 2.5V outputs
2.375 2.5 2.625 V
Power supply voltage for supporting 3.3V outputs
3.135 3.3 3.465 V
VDD33
Power supply voltage for core logic functions.
3.135 3.3* 3.465 V
VDDA
Analog power supply voltage. Use filtered analog power supply if
available.
2.375 3.465 V
VBAT
Battery power supply voltage.
2.8* 3* 3.465 V
Operating temperature, ambient -40 85 °C
CLOAD_OUT
Maximum load capacitance (3.3V LVCMOS only)
5pF
External reference crystal
840
External reference crystal with DCO used
12 38
External single-ended reference clock CLKINB
1125
External differential reference clock CLKIN, CLKINB
8125
tPU
Power up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic),
0.05 3 ms
* Power up Sequence Conditions
* VDDSEx for non 32KHz outputs should be OFF when VDDA/VDD3 turn OFF, VBAT mode only support 32.768KHz outputs from SE1~3
* Vbat power ramp up should be same or earlier than other Vdd power rail
MHzFIN
VDDSEx
* When use single-ended clock to CLKINB pin within differential clockin mode, CLKIN pin needs to be grounded and minimum input
frequency should be higher than 8MHz
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR 14 JANUARY 25, 2017
5P35021 DATASHEET
Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance
(TA = +25 °C)
Crystal Characteristics
Symbol
Parameter Min Typ Max Unit
CIN
Input Capacitance (CLKIN, CLKINB, OE, SDA, SCL,
DFC1:0)
37pF
Pull-down Resistor OE
200 k
LVCMOS Output Driver Impedance (VDDSE = 1.8V)
22
LVCMOS Output Driver Impedance (VDDSE = 2.5V)
22
LVCMOS Output Driver Impedance (VDDSE = 3.3V)
22
X1, X2
Programmable input capacitance at X1 or X2 0 15 pF
ROUT
Parameter Test Conditions Min Typ Max Units
Mode of Oscillation
Frequency 8 40 MHz
Frequency when 32.768K DCO is used 12 38 MHz
Equivalent Series Resistance (ESR) 10 100
Shunt Capacitance 2 7 pF
Load Capacitance (CL) 6 8 10 pF
Maximum Crystal Drive Level (CL=8pF) 100 µW
Fundamental
JANUARY 25, 2017 15 VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
5P35021 DATASHEET
DC Electrical Characteristics
Symbol Parameter Test Conditions Min Typ Max Unit
Iddcore Core Supply Current
VDD=VDDSE=VDD33=3.3V, Xtal=25Mhz, PLL2/3 OFF,
No Output - PLLs disabled
5mA
Idd_PLL1
3
PLL1 Supply Current
VDD=VDDSE=VDD33=3.3V, Xtal=25Mhz, PLL2/3 OFF,
No Output - PLL1= 600MHz
13 mA
VDD=VDDSE=VDD33=2.5V, Xtal=25Mhz, PLL2/3 OFF,
No Output - PLL1= 600MHz
13 mA
Idd_PLL2
3
PLL2 Supply Current
VDD=VDDSE=VDD33=3.3V, Xtal=25Mhz, PLL1/3 OFF,
No Output - PLL2=1GHz
11 mA
VDD=VDDSE=VDD33=2.5V, Xtal=25Mhz, PLL1/3 OFF,
No Output - PLL2=1GHz
11 mA
Idd_PLL3
3
PLL3 Supply Current
VDD=VDDSE=VDD33=3.3V, Xtal=25Mhz, PLL1/2 OFF,
No Output - PLL3=480
4mA
LVPECL, 500 MHz, 3.3V VDDDIFF (DIFF1,2) 39 mA
LVPECL, 156.25 MHz, 2.5V VDDDIFF (DIFF1,2) 33 mA
LVDS, 500 MHz, 3.3V VDDDIFF (DIFF1,2) 13 mA
LVDS, 250 MHz, 2.5V VDDDIFF (DIFF1,2) 8 mA
LPHCSL, 125MHz, 3.3V VDDDIFF, 2 pF load (DIFF1,2) 7 mA
LPHCSL, 100 MHz, 2.5V VDDDIFF, 2 pF load
(DIFF1 2)
8mA
LVCMOS, 8 MHz, 3.3V, VDDSE
1,2
(SE1)
1mA
LVCMOS, 8 MHz, 2.5V, VDDSE
1,2
(SE1)
1mA
LVCMOS, 8 MHz, 1.8V, VDDSE
1,2
(SE1)
1mA
LVCMOS, 160 MHz, 3.3V VDDSEx1 (SE1) 9.5 mA
LVCMOS, 160 MHz, 2.5V VDDSEx1,2 (SE1) 5.0 mA
LVCMOS, 160 MHz, 1.8V VDDSEx1,2 (SE1) 6.0 mA
Iddpd Power Down Current
PD asserted with VDDA, VDD33 and VDDSE ON, I2C
Programming, 32K running
3.5 mA
Iddsuspend -
VDD33
Iddsuspend-VBAT
Only VBAT=3.3V and VDDSEn is powered
1.1 µA
Iddsuspend -
SEn 3.3V
Iddsuspend - VDDSEn 3.3V
Only VBAT=3.3V and VDDSEn is powered with 3.3V
3.4 µA
Iddsuspend -
SEn 2.5V
Iddsuspend - VDDSEn 2.5V
Only VBAT =3.3Vand VDDSEn is powered with 2.5V
2.5 µA
Iddsuspend -
SEn 1.8V
Iddsuspend - VDDSEn 1.8V
Only VBAT=3.3V and VDDSEn is powered with 1.8V
1.8 µA
1. Single CMOS driver active.
2. SE1~3 current measured with 2 inches transmission line and 2 pF load, DIFF clock current measured with 5 inches transmission line with 2 pF loads.
3. Iddcore = IddA+ IddD, no loads.
Iddox Output Buffer Supply Current

5P35021-000NDGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products VersaClock 3S 5P25021 Prog. Clock
Lifecycle:
New from this manufacturer.
Delivery:
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