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5P35021-000NDGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR 28 JANUARY 25, 2017
5P35021 DATASHEET
Byte25: PLL2 charge pump control
Byte 19h Name Control Function Type 0 1 PWD
Bit 7 PLL2_CP_16X PLL2 charge pump control R/W - x16 0
Bit 6 PLL2_CP_8X PLL2 charge pump control R/W - x8 0
Bit 5 PLL2_CP_4X PLL2 charge pump control R/W - x4 1
Bit 4 PLL2_CP_2X PLL2 charge pump control R/W - x2 0
Bit 3 PLL2_CP_1X PLL2 charge pump control R/W - x1 0
Bit 2 PLL2_CP_/24 PLL2 charge pump control R/W - /24 1
Bit 1 PLL2_CP_/3 PLL2 charge pump control R/W - /3 0
Bit 0 PLL2_SIREF PLL2 SiRef current selection R/W 10uA 20uA 0
Byte26: PLL2 M divider setting
Byte 1Ah Name Control Function Type 0 1 PWD
Bit 7 PLL2_MDIV_Doubler PLL2 reference divider - doubler R/W disable enable 0
Bit 6 PLL2_MDIV1 PLL2 reference divider 1 R/W disable M DIV1 bypadd divider (/1) 1
Bit 5 PLL2_MDIV2 PLL2 reference divider 2 R/W disable M DIV2 bypadd divider (/2) 0
Bit 4 PLL2_MDIV[4] PLL2 reference divider control bit 4 R/W 0
Bit 3 PLL2_MDIV[3] PLL2 reference divider control bit 3 R/W 0
Bit 2 PLL2_MDIV[2] PLL2 reference divider control bit 2 R/W 0
Bit 1 PLL2_MDIV[1] PLL2 reference divider control bit 1 R/W 0
Bit 0 PLL2_MDIV[0] PLL2 reference divider control bit 0 R/W 0
Byte27: Output divider 4
Byte 1Bh Name Control Function Type 0 1 PWD
Bit 7 OUTDIV3[3] Out divider 3 control bit 7 R/W - - 0
Bit 6 OUTDIV3[2] Out divider 3 control bit 6 R/W - - 0
Bit 5 OUTDIV3[1] Out divider 3 control bit 5 R/W - - 1
Bit 4 OUTDIV3[0] Out divider 3 control bit 4 R/W - - 1
Bit 3 OUTDIV4[3] Out divider 4 control bit 3 R/W - - 0
Bit 2 OUTDIV4[2] Out divider 4 control bit 2 R/W - - 0
Bit 1 OUTDIV4[1] Out divider 4 control bit 1 R/W - - 1
Bit 0 OUTDIV4[0] Out divider 4 control bit 0 R/W - - 1
Byte28: PLL operation control register
Byte 1Ch Name Control Function Type 0 1 PWD
Bit 7 PLL2_HRS_EN PLL2 spread high resolution selection enable R/W notmal enable (shift 4 bits) 0
Bit 6 PLL2_refin_sel PLL2 reference clcok source select R/W Xtal DIV2 0
Bit 5 PLL3_PDB PLL3 Power Down R/W Power Down running 1
Bit 4 PLL3_LCKBYPSSB PLL3 lock bypass R/W bypass lock lock 1
Bit 3 PLL2_PDB PLL2 Power Down R/W Power Down running 1
Bit 2 PLL2_LCKBYPSSB PLL2 lock bypass R/W bypass lock lock 1
Bit 1 PLL1_PDB PLL1 Power Down R/W Power Down running 1
Bit 0 PLL1_LCKBYPSSB PLL1 lock bypass R/W bypass lock lock 1
Byte29: Output control
Byte 1Dh Name Control Function Type 0 1 PWD
Bit 7 DIFF1_SEL Differential clock 1 output OE2 control not controled controled 0
Bit 6 DIFF2_SEL Differential clock 2 output OE2 control not controled controled 0
Bit 5 DIFF1_EN Differential clock 1 output enable R/W disable enable 1
Bit 4 DIFF2_EN Differential clock 2 output enable R/W disable enable 1
Bit 3 OUTDIV4_Source Output divider 4 source clock selection R/W PLL2 Xtal 0
Bit 2 SE1_SLEW SE 1 slew rate control R/W normal strong 0
Bit 1 VDD1_SEL[1] VDD1 level control bit 1 R/W 0
Bit 0 VDD1_SEL[0] VDD1 level control bit 0 R/W 0
3~64, default is 25
00/01: 3.3V 10: 2.5V 11: 1.8
JANUARY 25, 2017 29 VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
5P35021 DATASHEET
Byte30: OE and DFC control
Byte 1Eh Name Control Function Type 0 1 PWD
Bit 7 SE1_EN SE1 output enable control R/W disable enable 1
Bit 6 OE1_fun_sel[1] OE1 pin function selection bit 1 R/W 0
Bit 5 OE1_fun_sel[0] OE1 pin function selection bit 0 R/W 0
Bit 4 * SE3_EN SE3 otuput enable R/W disable enable 1
Bit 3 * OE3_fun_sel[1] OE3 pin function selection bit 1 R/W 0
Bit 2 * OE3_fun_sel[0] OE3 pin function selection bit 0 R/W 0
Bit 1 * DFC_SW_Sel[1] DFC frequency select bit 1 R/W 0
Bit 0 * DFC_SW_Sel[0] DFC frequency select bit 0 R/W 0
Byte31: Control Register
Byte 1Fh Name Control Function Type 0 1 PWD
Bit 7 * SE2_Freerun_32K SE2 32K free run freerun 32K B31 bit6 control source 1
Bit 6 * SE2_CLKSEL1 SE2 source clock selection DIV5 DIV4 0
Bit 5 * VDD2_SEL[1] VDD2 level control bit 1 R/W 0
Bit 4 * VDD2_SEL[0] VDD2 level control bit 0 R/W 0
Bit 3 * SE2_SLEW SE 2 slew rate control R/W normal strong 0
Bit 2 PLL2_3rd_EN_CFG PLL2 3rd order control 1st order 3rd order 1
Bit 1 PLL2_EN_CH2 PLL2 channel 2 enable control R/W disable enable 0
Bit 0 PLL2_EN_3rdpole PLL2 3rd Pole control R/W disable enable 1
Byte32: Control Register
Byte 20h Name Control Function Type 0 1 PWD
Bit 7 * SE2_EN SE2 otuput enable R/W disable enable 1
Bit 6 * OE2_fun_sel[1] OE2 pin function selection bit 1 R/W 0
Bit 5 * OE2_fun_sel[0] OE2 pin function selection bit 0 R/W 0
Bit 4 DFC_EN DFC function control R/W disable enable 0
Bit 3 WD_EN WatchDog timer control R/W disable enable 0
Bit 2 Timer_sel<1> Watchdog timer select bit 1 R/W 0
Bit 1 Timer_sel<0> Watchdog timer select bit 0 R/W 0
Bit 0 Alarm_Flag Alarm Status(Read Only) R No alarm Alarmed 0
Byte33: SE3 and DIFF1 Control Register
Byte 21h Name Control Function Type 0 1 PWD
Bit 7 * SE3_Freerun_32K SE3 32K free run R/W freerun 32K DIV2 or DIV4 selected by B33bit6 1
Bit 6 * SE3_CLKSEL1 SE3 source clock selection R/W DIV2 DIV4 0
Bit 5 * VDD3_SEL[1] VDD3 level control bit 1 R/W 0
Bit 4 * VDD3_SEL[0] VDD3 level control bit 0 R/W 0
Bit 3 * SE3_SLEW SE 3 slew rate control R/W normal strong 0
Bit 2 DIFF_PDBHiZEN Differential output high-Z at power down R/W TBD output tri-state, bias off 0
Bit 1 DIFF1_CMOS2_FLIP Differential 1/2 LVCMOS otuput control R/W DIFF1_B inverted DIFF1_B non-inverted 0
Bit 0 DIFF2_CMOS2_FLIP Differential 1/2 LVCMOS otuput control R/W DIFF2_B inverted DIFF2_B non-inverted 0
Byte34: DIFF1 Control Register
Byte 22h Name Control Function Type 0 1 PWD
Bit 7 DIFF1_CLK_SEL Differential clock 1 source selection R/W DIV1 DIV3 1
Bit 6 DIFF1_io_pwr_sel Differential clock 1 output power R/W 2.5V 3.3V 1
Bit 5 DIFF1_OUTPUT_TYPE[1] Differential clock 1 type select bit 1 R/W 1
Bit 4 DIFF1_OUTPUT_TYPE[0] Differential clock 1 type select bit 0 R/W 1
Bit 3 DIFF1_AMP[1] Differential clock 1 amplitude control bit 1 R/W 0
Bit 2 DIFF1_AMP[0] Differential clock 1 amplitude control bit 0 R/W 1
Bit 1 DIFF1_CMOS_SLEW Differential clock 1 LVCMOS slew rate control R/W normal strong 0
Bit 0 D1FF1_CMOS2_EN Differential clock 1 LVCMOS output_B control R/W disable enable 0
11: 1.8V 10: 2.5V
0x: 3.3V
11:DFC0 10: SE1_PPS
01: PD# 00: SE1 OE
11: DFC1 10: SE3_PPS
01:xx 00:SE3_OE
00: N0 01: N1 10:N2 11:N3
00/01: 3.3V 10: 2.5V 11: 1.8
11: RESET 10: SE2_PPS
01: DIFF1/2 OE 00: SE2 OE
00: 250mS 01: 500ms
10: 2S 11: 4S
00: LVMOS 01: LVDS
10: LVPECL 11: LPHCSL
LPHCSL: 00=740mV,01=800mV,10=855mV,11=910mV
LPECL:00=710mV,01=810mV,10=875mV,11=920mV
LVDS:00=311mV,01=344mV,10=376mV,11=408mV
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR 30 JANUARY 25, 2017
5P35021 DATASHEET
Byte35: DIFF2 Control Register
Byte 23h Name Control Function Type 0 1 PWD
Bit 7 DIFF2_CLK_SEL Differential clock 2 source selection R/W DIV1 DIV3 0
Bit 6 DIFF2_IO_PWR_SEL Differential clock 2 output power R/W 2.5V 3.3V 1
Bit 5 DIFF2_OUTPUT_TYPE[1] Differential clock 2 type select bit 1 R/W 1
Bit 4 DIFF2_OUTPUT_TYPE[0] Differential clock 2 type select bit 0 R/W 1
Bit 3 DIFF2_AMP[1] Differential clock 2 amplitude control bit 1 R/W 0
Bit 2 DIFF2_AMP[0] Differential clock 2 amplitude control bit 0 R/W 1
Bit 1 DIFF2_CMOS_SLEW Differential clock 2 LVCMOS slew rate control R/W normal strong 0
Bit 0 DIFF2_CMOS2_EN Differential clock 2 LVCMOS output_B control R/W disable enable 0
Byte36: SE1 and DIV4 control
Byte 24h Name Control Function Type 0 1 PWD
Bit 7 I2C_PDB chip power down control bit R/W power dowm normal 1
Bit 6 Ref_free_run Reference clcok output (SE2/SE3) R/W stop freerun 0
Bit 5 free_run_output_config SE clocks free run control R/W SE2 free run SE2/3 free run 0
Bit 4 SE1_Freerun_32K SE1 clock output default R/W 32K freerun B36bit3 control 0
Bit 3 SE1_CLKSEL1 SEL1 output select R/W DIV5 DIV4 1
Bit 2 REF_EN REF output enable R/W disable enable 1
Bit 1 DIV4_CH3_EN DIV4 channel 3 output control R/W disable enable 0
Bit 0 DIV4_CH2_EN DIV4 channel 2 output control R/W disable enable 0
00: LVMOS 01: LVDS
10: LVPECL 11: LPHCSL
LPHCSL: 00=740mV,01=800mV,10=855mV,11=910mV
LPECL:00=710mV,01=810mV,10=875mV,11=920mV
LVDS:00=311mV,01=344mV,10=376mV,11=408mV
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

5P35021-000NDGI

Mfr. #:
Buy 5P35021-000NDGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products VersaClock 3S 5P25021 Prog. Clock
Lifecycle:
New from this manufacturer.
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