5P35021-000NDGI Datasheet 5P35021-000NDGI, 5P35021-000NDGI8 | P16-P18

VERSACLOCK

PROGRAMMABLE CLOCK GENERATOR 16 JANUARY 25, 2017

5P35021 DATASHEET

Power Consumption of 32.768kHz Output Only Operation

Unless stated otherwise, Supply Voltage VDDSE = 1.8V ~ 3.3V ±5%, TA = -40°C to +85°C

Electrical Characteristics – Input Parameters

1,2

Unless stated otherwise, Supply Voltage VDDD33 = 3.3V ±5%, TA = -40°C to +85°C

DC Electrical Characteristics for 3.3V LVCMOS

Unless stated otherwise, VDDSE = 3.3V±5%, TA = -40°C to +85°C

DC Electrical Characteristics for 2.5V LVCMOS

Unless stated otherwise, VDDSE = 2.5V±5%, TA = -40°C to +85°C

Symbol Parameter Test Conditions Min Typ Max Unit

I_VBAT Vbat=3.3V power input current 1.1 uA

I_VDDSEx VDDSEx=1.8V current

0.5 inch, no load, one output

0.4 uA

I_VDDSEx VDDSEx=1.8V current

2.0 inch, no load, one output

1.0 uA

I_VDDSEx VDDSEx=1.8V current

5.0 inch, no load, one output

2.3 uA

I_VDDSEx VDDSEx=2.5V current

0.5 inch, no load, one output

0.6 uA

I_VDDSEx VDDSEx=2.5V current

2.0 inch, no load, one output

1.5 uA

I_VDDSEx VDDSEx=2.5V current

5.0 inch, no load, one output

3.1 uA

I_VDDSEx VDDSEx=3.3V current

0.5 inch, no load, one output

0.8 uA

I_VDDSEx VDDSEx=3.3V current

2.0 inch, no load, one output

1.9 uA

I_VDDSEx VDDSEx=3.3V current

5.0 inch, no load, one output

4.2 uA

Symbol Parameter Test Conditions Min Typ Max Unit

VIH Input High Voltage - CLKIN Single-ended input 2.4 3.345 V

VIL Input Low Voltage - CLKIN Single-ended input GND - 0.3 0.8 V

VSWING

Input Amplitude - CLKIN Differential Input 325 3300 mV

dv/dt Input Slew Rate - CLKIN Differential Input 0.4 8 V/ns

VCM Input Common Mode Voltage Differential Input 200mV 2500 mV

IIL Input Leakage Low Current for OE1 VIN = GND @ OE1 pin -150 5 µA

IIL Input Leakage Low Current for OE2/3 VIN = GND 5µA

IIH Input Leakage High Current for OE1/2/3 VIN = 3.465 20 µA

dTIN Input Duty Cycle Measurement from differential waveform 45 55 %

1. Guaranteed by design and characterization, not 100% tested in production.

2. Slew rate measured through ±75mV window centered around differential zero.

Symbol Parameter Test Conditions Min Typ Max Unit

VOH Output HIGH Voltage

IOH = -15mA

2.4 VDDSE V

VOL Output LOW Voltage

IOL = 15mA

0.4 V

IOZDD Output Leakage Current

Tri-state outputs, VDDSE = 3.465V

3µA

VIH Input HIGH Voltage

Single-ended inputs - CLKSEL, OE, SDA, SCL

2VDDSE + 0.3V

VIL Input LOW Voltage

Single-ended inputs - CLKSEL, OE, SDA, SCL

GND - 0.3 0.8 V

VIH Input HIGH Voltage

Single-ended input - XIN/CLKIN

2.4 VDD33 V

VIL Input LOW Voltage

Single-ended input - XIN/CLKIN

GND - 0.3 0.8 V

Symbol Parameter Test Conditions Min Typ Max Unit

VOH Output HIGH Voltage

IOH = -12mA

0.7xVDDSE VDDSE V

VOL Output LOW Voltage

IOL = 12mA

0.4 V

IOZDD Output Leakage Current

Tri-state outputs, VDDSE = 2.625V

3µA

VIH Input HIGH Voltage

Single-ended inputs - CLKSEL, OE, SDA, SCL

1.7 VDDSE + 0.3 V

VIL Input LOW Voltage

Single-ended inputs - CLKSEL, OE, SDA, SCL

GND - 0.3 0.8 V

JANUARY 25, 2017 17 VERSACLOCK

PROGRAMMABLE CLOCK GENERATOR

5P35021 DATASHEET

DC Electrical Characteristics for 1.8V LVCMOS

Unless stated otherwise, VDDSE = 1.8V±5%, TA = -40°C to +85°C

Electrical Characteristics–DIF 0.7V LPHCSL Differential Outputs

Unless stated otherwise, VDDDIFF = 3.3 V ±5%or 2.5V ±5%, TA= -40° to +85°C

Symbol Parameter Test Conditions Min Typ Max Unit

VOH Output HIGH Voltage

IOH = -8mA

0.7 xVDDSE VDDSE V

VOL Output LOW Voltage

IOL = 8mA

0.25 x VDDSE V

IOZDD Output Leakage Current

Tri-state outputs, VDDSE = 1.89V

3µA

VIH Input HIGH Voltage

Single-ended inputs - OE, SDA, SCL

0.65 * VDDSE VDDSE + 0.3 V

VIL Input LOW Voltage

Single-ended inputs - OE, SDA, SCL

GND - 0.3 0.35 * VDDSE V

Symbol Parameter Notes Min Typ Max Units

dV/dt Slew Rate 1,2,3,8 1 2.5 4 V/ns

∆dV/dt Slew Rate mismatch

1,2,3,8, at

<=200MHz

20 %

VHIGH Voltage High 1,6,7,8 660 800 1150 mV

VLOW Voltage Low 1,6 -150 0 150 mV

VMAX Maximum Voltage 1 1150 mV

VMIN Minimum Voltage 1 -300 mV

VSWING Voltage Swing 1,2,6 300 mV

VCROSS Crossing Voltage Value 1,4,6 250 360 550 mV

VCROSS Crossing Voltage variation 1,5 140 mV

Jitter-Cy/Cy Cycle to cycle jitter 1,2 10 pS

Jitter-STJ Jitter - Period Jitter 1,2 70 pS

Duty Cycle Duty Cycle 1,2 45 55 %

Measured

Frequency

LVHCSL at differential output 1,2 500 MHz

* differential clock amplitude setting 00.

Note 7. Measured with scope averaging off, using statistics function. Variation is difference between min. and max

Note 8. Scope average ON

Note 6: Measured from single-ended waveform.

Note 5: the total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (VCROSS

absolute) allowed. The intent is to limit VCROSS induced modulation by setting

VCROSS to be smaller than VCROSS absolute.

Note 4: VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

Note 3: Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

Note 1: Guaranteed by design and characterization. Not 100% tested in production

Note 2: Meas ured from differential waveform.

VERSACLOCK

PROGRAMMABLE CLOCK GENERATOR 18 JANUARY 25, 2017

5P35021 DATASHEET

DC Electrical Characteristics for LVDS

Unless stated otherwise, VDDDIFF = 3.3 V ±5%or 2.5V ±5%, TA= -40° to +85°C

DC Electrical Characteristics for LVPECL

Unless stated otherwise, VDDDIFF = 3.3 V ±5%or 2.5V ±5%, TA= -40° to +85°C

Symbol Parameter

Notes

Min Typ Max Unit

VOT (+) Differential Output Voltage for the TRUE binary state 247 454 mV

VOT (-) Differential Output Voltage for the FALSE binary state -247 -454 mV

VOT Change in VOT between Complimentary Output States 50 mV

VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.25 1.375 V

VOS Change in VOS between Complimentary Output States 50 mV

IOS VDDDIFF 924mA

IOSD VOUT- 612mA

Jitter-Cy/Cy Cycle to cycle jitter 1,2 20 pS

Jitter-STJ Jitter - ST 1,2 100 pS

Duty Cycle Duty Cycle 1,2 45 55 %

Measured

Frequency

LVDS at differential output 1,2 500 MHz

* differential clock amplitude setting 01.

Symbol Parameter

Notes

Min Typ Max Unit

VOH

Output Voltage HIGH, terminated through 50Ω tied to

VDDDIFF-2 V VDDDIFF - 1.19 VDDDIFF - 0.69 V

VOL

Output Voltage LOW, terminated through 50Ω tied to

VDDDIFF-2 V VDDDIFF - 1.94 VDDDIFF - 1.4 V

VSWING

Peak-to-Peak Output Voltage Swing 0.55 0.993 V

Jitter-Cy/Cy Cycle to cycle jitter 1,2 20 pS

Jitter-STJ Jitter - ST 1,2 100 pS

Duty Cycle Duty Cycle 1,2 45 55 %

Measured

Frequency

LVPECL at differential output 1,2 500 MHz

* differential clock amplitude setting 01.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P34

5P35021-000NDGI

Mfr. #:

Buy 5P35021-000NDGI

Manufacturer:

IDT

Description:

Clock Generators & Support Products VersaClock 3S 5P25021 Prog. Clock

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

5P35021-000NDGI

5P35021-000NDGI

Products related to this Datasheet