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5P35021-000NDGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR 22 JANUARY 25, 2017
5P35021 DATASHEET
General I2C Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Note: SE2/SE3 function setting is not available on
5P35021 in QFN20 package, For full SE1~SE3 outputs
requirements and functionality, please refer to the
5P35023 datasheet.
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
JANUARY 25, 2017 23 VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
5P35021 DATASHEET
Byte0: General Control
B
y
te 00h Name Control Function T
yp
e0 1PWD
Bit 7 OTP_Burned OTP memory programming indication R/W OTP memory non-programmed OTP memory programmed 0
Bit 6 I2C_addr[1] I2C address select bit 1 R/W 0
Bit 5 I2C_addr[0] I2C address select bit 0 R/W 0
Bit 4 PLL1_SSEN PLL1 Spread Spectrum enable R/W disable enable 0
Bit 3 DIV1_src_sel Divider 1 source clock select R/W PLL1 Xtal 0
Bit 2 PLL3_refin_sel PLL3 source selection R/W Xtal Seed (DIV2) 0
Bit 1 EN_CLKIN enable CLKIN R/W disable enable 0
Bit 0 OTP_protect OTP memory protection R/W read/write write locked 0
Byte1: Dash Code ID (optional)
Byte 01h Name Control Function Type 0 1 PWD
Bit 7 DashCode ID[7] Dash code ID R/W - - 0
Bit 6 DashCode ID[6] Dash code ID R/W - - 0
Bit 5 DashCode ID[5] Dash code ID R/W - - 0
Bit 4 DashCode ID[4] Dash code ID R/W - - 0
Bit 3 DashCode ID[3] Dash code ID R/W - - 0
Bit 2 DashCode ID[2] Dash code ID R/W - - 0
Bit 1 DashCode ID[1] Dash code ID R/W - - 0
Bit 0 DashCode ID[0] Dash code ID R/W - - 0
Byte2: Crystal Cap setting
Byte 02h Name Control Function Type 0 1 PWD
Bit 7 Xtal_Cap[7] Xtal cap load trimming bits R/W 0
Bit 6 Xtal_Cap[6] Xtal cap load trimming bits R/W 0
Bit 5 Xtal_Cap[5] Xtal cap load trimming bits R/W 0
Bit 4 Xtal_Cap[4] Xtal cap load trimming bits R/W 1
Bit 3 Xtal_Cap[3] Xtal cap load trimming bits R/W 0
Bit 2 Xtal_Cap[2] Xtal cap load trimming bits R/W 0
Bit 1 Xtal_Cap[1] Xtal cap load trimming bits R/W 0
Bit 0 Xtal_Cap[0] Xtal cap load trimming bits R/W 1
Byte3: PLL3 M Divider
Byte 03h Name Control Function Type 0 1 PWD
Bit 7 PLL3_MDIV1 PLL3 source clock divider R/W disable M DIV1 bypadd divider (/1) 0
Bit 6 PLL3_MDIV2 PLL3 source clock divider R/W disable M DIV2 bypadd divider (/2) 0
Bit 5 PLL3 M_DIV[5] PLL3 reference integer divider R/W 3~64 default 25 0
Bit 4 PLL3 M_DIV[4] PLL3 reference integer divider R/W - - 1
Bit 3 PLL3 M_DIV[3] PLL3 reference integer divider R/W - - 1
Bit 2 PLL3 M_DIV[2] PLL3 reference integer divider R/W - - 0
Bit 1 PLL3 M_DIV[1] PLL3 reference integer divider R/W - - 0
Bit 0 PLL3 M_DIV[0] PLL3 reference integer divider R/W - - 1
Byte4: PLL3 N Divider
Byte 04h Name Control Function Type 0 1 PWD
Bit 7 PLL3 N_DIV[7] PLL3 VCO feedback integer divider bit7 R/W 1
Bit 6 PLL3 N_DIV[6] PLL3 VCO feedback integer divider bit6 R/W 1
Bit 5 PLL3 N_DIV[5] PLL3 VCO feedback integer divider bit5 R/W 1
Bit 4 PLL3 N_DIV[4] PLL3 VCO feedback integer divider bit4 R/W 0
Bit 3 PLL3 N_DIV[3] PLL3 VCO feedback integer divider bit3 R/W 0
Bit 2 PLL3 N_DIV[2] PLL3 VCO feedback integer divider bit2 R/W 0
Bit 1 PLL3 N_DIV[1] PLL3 VCO feedback integer divider bit1 R/W 0
Bit 0 PLL3 N_DIV[0] PLL3 VCO feedback integer divider bit0 R/W 0
00: D0 / 01: D2
10: D4 / 11: D6
x1 x2
x4 x8
total 15pf
12~2048, default VCO setting is 480MHz
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR 24 JANUARY 25, 2017
5P35021 DATASHEET
Byte5: PLL3 Loop filter setting and N Divider10:8
Byte 05h Name Control Function Type 0 1 PWD
Bit 7 PLL3_R100K PLL3 Loop filter resister 100Kohm R/W bypass plus 100Kohm 0
Bit 6 PLL3_R50K PLL3 Loop filter resister 50Kohm R/W bypass plus 50Kohm 0
Bit 5 PLL3_R25K PLL3 Loop filter resister 25Kohm R/W bypass plus 25Kohm 0
Bit 4 PLL3_R12.5K PLL3 Loop filter resister 12.5Kohm R/W bypass plus 12.5Kohm 1
Bit 3 PLL3_R6K PLL3 Loop filter resister 6Kohm R/W bypass only 6Kohm applied 0
Bit 2 PLL3 N_DIV[10] PLL3 VCO feedback integer divider bit10 R/W 0
Bit 1 PLL3 N_DIV[9] PLL3 VCO feedback integer divider bit9 R/W 0
Bit 0 PLL3 N_DIV[8] PLL3 VCO feedback integer divider bit8 R/W 1
Byte6: PLL3 charge pump control
Byte 06h Name Control Function Type 0 1 PWD
Bit 7
OUTDIV3Source Outputdivide r3sourceclockselection R/W PLL2 PLL3 0
Bit 6 PLL3_CP_8X PLL3 charge pump control R/W - x8 1
Bit 5 PLL3_CP_4X PLL3 charge pump control R/W - x4 1
Bit 4 PLL3_CP_2X PLL3 charge pump control R/W - x2 0
Bit 3 PLL3_CP_1X PLL3 charge pump control R/W - x1 1
Bit 2 PLL3_CP_/24 PLL3 charge pump control R/W - /24 1
Bit 1 PLL3_CP_/3 PLL3 charge pump control R/W - /3 0
Bit 0 PLL3_SIREF PLL3 SiRef current selection R/W 10uA 20uA 0
Notes: Formula : (iRef (10uA) * (1+SIREF) *(1*1X+2*2X+4*4X+8*8X+16*16X))/((24*/24)+(3*/3))
Byte7: PLL1 Control and OUTDIV5 divider
Byte 07h Name Control Function Type 0 1 PWD
Bit 7 PLL1_MDIV_Doubler PLL1 reference clock doubler R/W disable enable 0
Bit 6 PLL1_SIREF PLL1 SiRef current selection R/W 10.8uA 21.6uA 0
Bit 5 PLL1_EN_CH2 PLL1 output Channel 2 control R/W disable enable 1
Bit 4 PLL1_EN_3rdpole PLL1 3rd Pole control R/W disable enable 0
Bit 3 OUTDIV5[3] Output divider5 control bit 3 R/W - - 0
Bit 2 OUTDIV5[2] Output divider5 control bit 2 R/W - - 0
Bit 1 OUTDIV5[1] Output divider5 control bit 1 R/W - - 1
Bit 0 OUTDIV5[0] Output divider5 control bit 0 R/W - - 1
Byte8: PLL1 M Divider
Byte 08h Name Control Function Type 0 1 PWD
Bit 7 PLL1_MDIV1 PLL3 VCO referenceclock divider 1 R/W disable M DIV1 bypass divider (/1) 0
Bit 6 PLL1_MDIV2 PLL3 VCO referenceclock divider 2 R/W disable M DIV2 bypass divider (/2) 0
Bit 5 PLL1 M_DIV[5] PLL1 reference clock divider control bit 5 R/W 0
Bit 4 PLL1 M_DIV[4] PLL1 reference clock divider control bit 4 R/W 1
Bit 3 PLL1 M_DIV[3] PLL1 reference clock divider control bit 3 R/W 1
Bit 2 PLL1 M_DIV[2] PLL1 reference clock divider control bit 2 R/W 0
Bit 1 PLL1 M_DIV[1] PLL1 reference clock divider control bit 1 R/W 0
Bit 0 PLL1 M_DIV[0] PLL1 reference clock divider control bit 0 R/W 1
Byte9: PLL1 VCO N divider
Byte 09h Name Control Function Type 0 1 PWD
Bit 7 PLL1 N_DIV[7] PLL1 VCO feedback divider control bit 7 R/W 0
Bit 6 PLL1 N_DIV[6] PLL1 VCO feedback divider control bit 6 R/W 1
Bit 5 PLL1 N_DIV[5] PLL1 VCO feedback divider control bit 5 R/W 0
Bit 4 PLL1 N_DIV[4] PLL1 VCO feedback divider control bit 4 R/W 1
Bit 3 PLL1 N_DIV[3] PLL1 VCO feedback divider control bit 3 R/W 1
Bit 2 PLL1 N_DIV[2] PLL1 VCO feedback divider control bit 2 R/W 0
Bit 1 PLL1 N_DIV[1] PLL1 VCO feedback divider control bit 1 R/W 0
Bit 0 PLL1 N_DIV[0] PLL1 VCO feedback divider control bit 0 R/W 0
12~2048, default VCO setting is 480MHz
3~64, default is 25
12~2048, default is 600
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

5P35021-000NDGI

Mfr. #:
Buy 5P35021-000NDGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products VersaClock 3S 5P25021 Prog. Clock
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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