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5P35021-000NDGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
JANUARY 25, 2017 25 VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
5P35021 DATASHEET
Byte10: PLL loop filterand N divider
Byte 0Ah Name Control Function Type 0 1 PWD
Bit 7 PLL1_R100K PLL1 Loop filter resister 100Kohm R/W bypass plus 100Kohm 1
Bit 6 PLL1_R50K PLL1 Loop filter resister 50Kohm R/W bypass plus 50Kohm 0
Bit 5 PLL1_R25K PLL1 Loop filter resister 25Kohm R/W bypass plus 25Kohm 1
Bit 4 PLL1_R12.5K PLL1 Loop filter resister 12.5Kohm R/W bypass plus 12.5Kohm 1
Bit 3 PLL1_R1.0K PLL1 Loop filter resister 1Kohm R/W bypass only 1.0Kohm applied 0
Bit 2 PLL1 N_DIV[10] PLL1 VCO feedback integer divider bit10 R/W 0
Bit 1 PLL1 N_DIV[9] PLL1 VCO feedback integer divider bit9 R/W 1
Bit 0 PLL1 N_DIV[8] PLL1 VCO feedback integer divider bit8 R/W 0
Byte11: PLL1 charge pump
Byte 0Bh Name Control Function Type 0 1 PWD
Bit 7 PLL1_CP_32X PLL1 charge pump control R/W - x32 0
Bit 6 PLL1_CP_16X PLL1 charge pump control R/W - x16 0
Bit 5 PLL1_CP_8X PLL1 charge pump control R/W - x8 0
Bit 4 PLL1_CP_4X PLL1 charge pump control R/W - x4 0
Bit 3 PLL1_CP_2X PLL1 charge pump control R/W - x2 0
Bit 2 PLL1_CP_1X PLL1 charge pump control R/W - x1 1
Bit 1 PLL1_CP_/24 PLL1 charge pump control R/W - /24 1
Bit 0 PLL1_CP_/3 PLL1 charge pump control R/W - /3 0
Byte12: PLL1 spread spectrum control
Byte 0Ch Name Control Function Type 0 1 PWD
Bit 7 PLL1_SS_REFDIV23 PLL1 Spread Spectrum control- Ref divider 23 R/W - - 0
Bit 6 PLL1_SS_REFDIV[6] PLL1 Spread Spectrum control- Ref divider 6 R/W - - 0
Bit 5 PLL1_SS_REFDIV[5] PLL1 Spread Spectrum control- Ref divider 5 R/W - - 0
Bit 4 PLL1_SS_REFDIV[4] PLL1 Spread Spectrum control- Ref divider 4 R/W - - 0
Bit 3 PLL1_SS_REFDIV[3] PLL1 Spread Spectrum control- Ref divider 3 R/W - - 0
Bit 2 PLL1_SS_REFDIV[2] PLL1 Spread Spectrum control- Ref divider 2 R/W - - 0
Bit 1 PLL1_SS_REFDIV[1] PLL1 Spread Spectrum control- Ref divider 1 R/W - - 0
Bit 0 PLL1_SS_REFDIV[0] PLL1 Spread Spectrum control- Ref divider 0 R/W - - 0
Byte13: PLL1 spread spectrum control
Byte 0Dh Name Control Function Type 0 1 PWD
Bit 7 PLL1_SS_FBDIV[7] PLL1 Spread Spectrum - feedback divider 7 R/W - - 0
Bit 6 PLL1_SS_FBDIV[6] PLL1 Spread Spectrum - feedback divider 6 R/W - - 0
Bit 5 PLL1_SS_FBDIV[5] PLL1 Spread Spectrum - feedback divider 5 R/W - - 0
Bit 4 PLL1_SS_FBDIV[4] PLL1 Spread Spectrum - feedback divider 4 R/W - - 0
Bit 3 PLL1_SS_FBDIV[3] PLL1 Spread Spectrum - feedback divider 3 R/W - - 0
Bit 2 PLL1_SS_FBDIV[2] PLL1 Spread Spectrum - feedback divider 2 R/W - - 0
Bit 1 PLL1_SS_FBDIV[1] PLL1 Spread Spectrum - feedback divider 1 R/W - - 0
Bit 0 PLL1_SS_FBDIV[0] PLL1 Spread Spectrum - feedback divider 0 R/W - - 0
Byte14: PLL1 Spread spectrum control
Byte 0Eh Name Control Function Type 0 1 PWD
Bit 7 PLL1_SS_FBDIV[15] PLL1 Spread Spectrum - feedback divider 15 R/W - - 0
Bit 6 PLL1_SS_FBDIV[14] PLL1 Spread Spectrum - feedback divider 14 R/W - - 0
Bit 5 PLL1_SS_FBDIV[13] PLL1 Spread Spectrum - feedback divider 13 R/W - - 0
Bit 4 PLL1_SS_FBDIV[12] PLL1 Spread Spectrum - feedback divider 12 R/W - - 0
Bit 3 PLL1_SS_FBDIV[11] PLL1 Spread Spectrum - feedback divider 11 R/W - - 0
Bit 2 PLL1_SS_FBDIV[10] PLL1 Spread Spectrum - feedback divider 10 R/W - - 0
Bit 1 PLL1_SS_FBDIV[09] PLL1 Spread Spectrum - feedback divider 9 R/W - - 0
Bit 0 PLL1_SS_FBDIV[08] PLL1 Spread Spectrum - feedback divider 8 R/W - - 0
'12~2048, default is 600
VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR 26 JANUARY 25, 2017
5P35021 DATASHEET
Byte15: Output divider1 control
Byte 0Fh Name Control Function Type 0 1 PWD
Bit 7 OUTDIV1[3] Output divider1 control bit 3 R/W - - 0
Bit 6 OUTDIV1[2] Output divider1 control bit 2 R/W - - 0
Bit 5 OUTDIV1[1] Output divider1 control bit 1 R/W - - 1
Bit 4 OUTDIV1[0] Output divider1 control bit 0 R/W - - 1
Bit 3 OUTDIV2[3] Output divider2 control bit 3 R/W - - 0
Bit 2 OUTDIV2[2] Output divider2 control bit 2 R/W - - 0
Bit 1 OUTDIV2[1] Output divider2 control bit 1 R/W - - 1
Bit 0 OUTDIV2[0] Output divider2 control bit 0 R/W - - 1
Byte16: PLL2 integer feedback divider
Byte 10h Name Control Function Type 0 1 PWD
Bit 7 reserved - R/W - - 0
Bit 6 reserved - R/W - - 0
Bit 5 reserved - R/W - - 0
Bit 4 reserved - R/W - - 0
Bit 3 reserved - R/W - - 0
Bit 2 PLL2_FB_INT[10] PLL2 feedback integer divier 10 R/W - - 0
Bit 1 PLL2_FB_INT[9] PLL2 feedback integer divier 9 R/W - - 0
Bit 0 PLL2_FB_INT[8] PLL2 feedback integer divier 8 R/W - - 0
Byte17: PLL2 integer feedback divider
Byte 11h Name Control Function Type 0 1 PWD
Bit 7 PLL2_FB_INT_DIV[7] PLL2 feedback integer divier 7 R/W - - 0
Bit 6 PLL2_FB_INT_DIV[6] PLL2 feedback integer divier 6 R/W - - 0
Bit 5 PLL2_FB_INT_DIV[5] PLL2 feedback integer divier 5 R/W - - 1
Bit 4 PLL2_FB_INT_DIV[4] PLL2 feedback integer divier 4 R/W - - 0
Bit 3 PLL2_FB_INT_DIV[3] PLL2 feedback integer divier 3 R/W - - 1
Bit 2 PLL2_FB_INT_DIV[2] PLL2 feedback integer divier 2 R/W - - 0
Bit 1 PLL2_FB_INT_DIV[1] PLL2 feedback integer divier 1 R/W - - 0
Bit 0 PLL2_FB_INT_DIV[0] PLL2 feedback integer divier 0 R/W - - 0
Byte18: PLL2 fractional feedback divider
Byte 12h Name Control Function Type 0 1 PWD
Bit 7 PLL2_FB_FRC_DIV[7] PLL2 feedback fractional divier 7 R/W - - 0
Bit 6 PLL2_FB_FRC_DIV[6] PLL2 feedback fractional divier 6 R/W - - 0
Bit 5 PLL2_FB_FRC_DIV[5] PLL2 feedback fractional divier 5 R/W - - 0
Bit 4 PLL2_FB_FRC_DIV[4] PLL2 feedback fractional divier 4 R/W - - 0
Bit 3 PLL2_FB_FRC_DIV[3] PLL2 feedback fractional divier 3 R/W - - 0
Bit 2 PLL2_FB_FRC_DIV[2] PLL2 feedback fractional divier 2 R/W - - 0
Bit 1 PLL2_FB_FRC_DIV[1] PLL2 feedback fractional divier 1 R/W - - 0
Bit 0 PLL2_FB_FRC_DIV[0] PLL2 feedback fractional divier 0 R/W - - 0
Byte19: PLL2 fractional feedback divider
Byte 13h Name Control Function Type 0 1 PWD
Bit 7 PLL2_FB_FRC_DIV[15] PLL2 feedback fractional divier 15 R/W - - 0
Bit 6 PLL2_FB_FRC_DIV[14] PLL2 feedback fractional divier 14 R/W - - 0
Bit 5 PLL2_FB_FRC_DIV[13] PLL2 feedback fractional divier 13 R/W - - 0
Bit 4 PLL2_FB_FRC_DIV[12] PLL2 feedback fractional divier 12 R/W - - 0
Bit 3 PLL2_FB_FRC_DIV[11] PLL2 feedback fractional divier 11 R/W - - 0
Bit 2 PLL2_FB_FRC_DIV[10] PLL2 feedback fractional divier 10 R/W - - 0
Bit 1 PLL2_FB_FRC_DIV[9] PLL2 feedback fractional divier 9 R/W - - 0
Bit 0 PLL2_FB_FRC_DIV[8] PLL2 feedback fractional divier 8 R/W - - 0
JANUARY 25, 2017 27 VERSACLOCK
®
PROGRAMMABLE CLOCK GENERATOR
5P35021 DATASHEET
Byte20: PLL2 spread spectrum control
Byte 14h Name Control Function Type 0 1 PWD
Bit 7 PLL2_STEP[7] PLL2 spread step size control bit 7 R/W - - 0
Bit 6 PLL2_STEP[6] PLL2 spread step size control bit 6 R/W - - 0
Bit 5 PLL2_STEP[5] PLL2 spread step size control bit 5 R/W - - 0
Bit 4 PLL2_STEP[4] PLL2 spread step size control bit 4 R/W - - 0
Bit 3 PLL2_STEP[3] PLL2 spread step size control bit 3 R/W - - 0
Bit 2 PLL2_STEP[2] PLL2 spread step size control bit 2 R/W - - 0
Bit 1 PLL2_STEP[1] PLL2 spread step size control bit 1 R/W - - 0
Bit 0 PLL2_STEP[0] PLL2 spread step size control bit 0 R/W - - 0
Byte21: PLL2 spread spectrum control
Byte 15h Name Control Function Type 0 1 PWD
Bit 7 PLL2_STEP[15] PLL2 spread step size control bit 15 R/W - - 0
Bit 6 PLL2_STEP[14] PLL2 spread step size control bit 14 R/W - - 0
Bit 5 PLL2_STEP[13] PLL2 spread step size control bit 13 R/W - - 0
Bit 4 PLL2_STEP[12] PLL2 spread step size control bit 12 R/W - - 0
Bit 3 PLL2_STEP[11] PLL2 spread step size control bit 11 R/W - - 0
Bit 2 PLL2_STEP[10] PLL2 spread step size control bit 10 R/W - - 0
Bit 1 PLL2_STEP[9] PLL2 spread step size control bit 9 R/W - - 0
Bit 0 PLL2_STEP[8] PLL2 spread step size control bit 8 R/W - - 0
Byte22: PLL2 spread spectrum control
Byte 16h Name Control Function Type 0 1 PWD
Bit 7 PLL2_STEP_DELTA[7] PLL2 spread step size control delta bit 7 R/W - - 0
Bit 6 PLL2_STEP_DELTA[6] PLL2 spread step size control delta bit 6 R/W - - 0
Bit 5 PLL2_STEP_DELTA[5] PLL2 spread step size control delta bit 5 R/W - - 0
Bit 4 PLL2_STEP_DELTA[4] PLL2 spread step size control delta bit 4 R/W - - 0
Bit 3 PLL2_STEP_DELTA[3] PLL2 spread step size control delta bit 3 R/W - - 0
Bit 2 PLL2_STEP_DELTA[2] PLL2 spread step size control delta bit 2 R/W - - 0
Bit 1 PLL2_STEP_DELTA[1] PLL2 spread step size control delta bit 1 R/W - - 0
Bit 0 PLL2_STEP_DELTA[0] PLL2 spared step size control delta bit 0 R/W - - 0
Byte23: PLL2 period control
Byte 17h Name Control Function Type 0 1 PWD
Bit 7 PLL2_PERIOD[7] PLL2 period control bit 7 R/W - - 0
Bit 6 PLL2_PERIOD[6] PLL2 period control bit 6 R/W - - 0
Bit 5 PLL2_PERIOD[5] PLL2 period control bit 5 R/W - - 0
Bit 4 PLL2_PERIOD[4] PLL2 period control bit 4 R/W - - 0
Bit 3 PLL2_PERIOD[3] PLL2 period control bit 3 R/W - - 0
Bit 2 PLL2_PERIOD[2] PLL2 period control bit 2 R/W - - 0
Bit 1 PLL2_PERIOD[1] PLL2 period control bit 1 R/W - - 0
Bit 0 PLL2_PERIOD[0] PLL2 period control bit 0 R/W - - 0
Byte24: PLL2 control register
Byte 18h Name Control Function Type 0 1 PWD
Bit 7 PLL2_PERIOD[9] PLL2 period control bit 9 R/W - - 0
Bit 6 PLL2_PERIOD[8] PLL2 period control bit 8 R/W - - 0
Bit 5 PLL2_SSEN PLL2 spread spectrum enable R/W disable enable 0
Bit 4 PLL2_R100K PLL2 Loop filter resister 100Kohm bypass plus 100Kohm 0
Bit 3 PLL2_R50K PLL2 Loop filter resister 50Kohm bypass plus 50Kohm 0
Bit 2 PLL2_R25K PLL2 Loop filter resister 25Kohm bypass plus 25Kohm 0
Bit 1 PLL2_R12.5K PLL2 Loop filter resister 12.5Kohm bypass plus 12.5Kohm 0
Bit 0 PLL2_R6K PLL2 Loop filter resister 6Kohm bypass only 6Kohm applied 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

5P35021-000NDGI

Mfr. #:
Buy 5P35021-000NDGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products VersaClock 3S 5P25021 Prog. Clock
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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