Symbol Parameter Test Conditions Min. Typ. Max. Units
Input frequency limit (XIN) 8 40 MHz
Input frequency limit (XIN) when enable DCO 12 38 MHz
Input frequency limit (Differential CLKIN) 8 125 MHz
Input frequency limit (LVCMOS to X1) 1 125 MHz
Single ended clock output limit (LVCMOS) 1 <125 160 MHz
Differential clock output limit (LPHCSL) 1 <333 500 MHz
Differential clock output limit (LVDS) 1 <333 500 MHz
Differential clock output limit (LVPECL) 1 500 MHz
fVCO1 VCO frequency range of PLL1 VCO operating frequency range 300 600 MHz
fVCO2 VCO frequency range of PLL2 VCO operating frequency range 400 1200 MHz
fVCO3 VCO frequency range of PLL3 VCO operating frequency range 300 800 MHz
t2 Input Duty Cycle Duty Cycle 45 55 %
t3 Output Duty Cycle
LVCMOS and Differential clock <333MHz ,
Crossing point measurements
45 55 %
t3 Output Duty Cycle
LVCMOS and Differential clock >333MHz ,
Crossing point measurements
40 60 %
t3 Output Duty Cycle_REF Reference clock output or SE1~3 fan out clock 40 60 %
Rise/Fall, SLEW[0] = 1
Single-ended LVCMOS output clock rise and fall
time, 20% to 80% of VDDSE1.8V~3.3V 1.0
Rise/Fall, SLEW[0] = 0
Single-ended LVCMOS output clock rise and fall
time, 20% to 80% of VDDSE1.8V~3.3V 1.1
Rise Times LVDS, 20% to 80% 300
Fall Times LVDS, 80% to 20% 300
Rise Times LVPECL, 20% to 80% 300
Fall Times LVPECL, 80% to 20% 300
Cycle-to-Cycle jitter (Peak-to-Peak), multiple
output frequencies switching, differential outputs
(1.8V to 3.3V nominal output voltage)
SE1=25MHz
*SE2=100MHz
*SE3=100MHz
DIFF1/2=100MHz
50 ps
RMS Phase Jitter (12kHz to 20MHz integration
range) differential output, VDDSE = 3.465V,
25MHz crystal,
SE1=25MHz
*SE2=100MHz
*SE3=100MHz
DIFF1/2=100MHz
1.1 ps
t7 Output Skew
Skew between the same frequencies, with outputs
using the same driver format
75 ps
t8 2 Lock Time PLL lock time from power-up 20 ms
t9 Lock Time 32.768KHz clock Low Power power-up Time 10 100 ms
t9 3 Lock Time PLL lock time from shutdown mode 0.1 2 ms
4. * SE2/SE3 are not available in 5P35021, only available in 5P35023 QFN24 device
5. t4 Rise/Fall time measurements are based on 5pF load
6. t5 Rise/Fall time measurements are based on 2pF load
Input FrequencyfIN 1
Output FrequencyfOUT
1. Practical lower frequency is determined by loop filter settings.
2. Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.
3. Actual PLL lock time depends on the loop configuration.
t4 nS
t5 ps
t6 Clock Jitter
