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LPC2458FET180,551

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81
LPC2458 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 15 October 2013 19 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
P4[31]/CS1 E7
[1]
I/O P4[31] — General purpose digital input/output pin.
O CS1
— LOW active Chip Select 1 signal.
ALARM H5
[7]
O ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC
alarm is generated.
USB_D2N2I/OUSB_D2 — USB port 2 bidirectional D line.
DBGEN E5
[1][8]
I DBGEN — JTAG interface control signal. Also used for boundary scan.
TDO B1
[1][9]
O TDO — Test Data Out for JTAG interface.
TDI C3
[1][8]
I TDI — Test Data In for JTAG interface.
TMS C2
[1][8]
I TMS — Test Mode Select for JTAG interface.
TRST
D4
[1][8]
I TRST — Test Reset for JTAG interface.
TCK D2
[1][9]
I TCK — Test Clock for JTAG interface. This clock must be slower than
1
⁄
6
of the
CPU clock (CCLK) for the JTAG interface to operate.
RTCK C4
[1][8]
I/O RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET
is LOW enables ETM pins (P2[9:0]) to
operate as Trace port after reset.
RSTOUT
H2 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2458 being in
Reset state.
RESET
J1
[10]
I external reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 L2
[7][11]
I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 K4
[7][11]
O Output from the oscillator amplifier.
RTCX1 J2
[7][12]
I Input to the RTC oscillator circuit.
RTCX2 J3
[7][12]
O Output from the RTC oscillator circuit.
V
SSIO
H4, P4,
L9, L13,
G13,
D13,
C11,
B4
[13]
I ground: 0 V reference for the digital IO pins.
V
SSCORE
H3, L8,
A10
[13]
I ground: 0 V reference for the core.
V
SSA
F3
[14]
I analog ground: 0 V reference. This should nominally be the same voltage as
V
SSIO
/V
SSCORE
, but should be isolated to minimize noise and error.
V
DD(3V3)
E2, L4,
K8, L11,
J14, E12,
E10,
C5
[15]
I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
n.c. H1, L12,
G10
[16]
I not connected pins: These pins must be left unconnected (floating).
V
DD(DCDC)(3V3)
G1, N9,
E9
[17]
I 3.3 V DC-to-DC converter supply voltage: This is the power supply for the
on-chip DC-to-DC converter.
Table 4. Pin description …continued
Symbol Ball Type Description
LPC2458 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 15 October 2013 20 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I
2
C-bus 400 kHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I
2
C-bus is floating and does not disturb the I
2
C lines. Open-drain
configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7] Pad provides special analog functionality.
[8] This pin has a built-in pull-up resistor.
[9] This pin has no built-in pull-up and no built-in pull-down resistor.
[10] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
[12] If the RTC is not used, these pins can be left floating.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.
[15] Pad provides special analog functionality.
[16] Pad provides special analog functionality.
[17] Pad provides special analog functionality.
[18] Pad provides special analog functionality.
7. Functional description
7.1 Architectural overview
The LPC2458 microcontroller consists of an ARM7TDMI-S CPU with emulation support,
the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip
memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external
memory, and the AMBA APB for connection to other on-chip peripheral functions. The
microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte
order.
The LPC2458 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1,
includes the VIC, GPDMA controller, and EMC.
V
DDA
F2
[18]
I analog 3.3 V pad supply voltage: This should be nominally the same voltage as
V
DD(3V3)
but should be isolated to minimize noise and error. This voltage is used
to power the ADC and DAC.
VREF G2
[18]
I ADC reference: This should be nominally the same voltage as V
DD(3V3)
but
should be isolated to minimize noise and error. The level on this pin is used as a
reference for ADC and DAC.
VBAT K1
[18]
I RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
Table 4. Pin description …continued
Symbol Ball Type Description
LPC2458 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 15 October 2013 21 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,
and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2
are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB. The
AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a
2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is
allocated a 16 kB address space within the APB address space.
The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers
high performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed complex
instruction set computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• the standard 32-bit ARM set
• a 16-bit Thumb set
The Thumb set’s 16-bit instruction length allows it to approach higher density compared to
standard ARM code while retaining most of the ARM’s performance.
7.2 On-chip flash programming memory
The LPC2458 incorporates 512 kB flash memory system. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port (UART0). The
application program may also erase and/or program the flash while the application is
running, allowing a great degree of flexibility for data storage field and firmware upgrades.
The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at speeds of 72 MHz.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81

LPC2458FET180,551

Mfr. #:
Buy LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 512KF/USBH/ENET
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New from this manufacturer.
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