LPC2458 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 15 October 2013 5 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
6. Pinning information
6.1 Pinning
Fig 2. LPC2458 pinning TFBGA180 package
002aad094
LPC2458
2 4 6 8 10 12 13 141357911
ball A1
index area
P
N
M
L
K
J
G
E
H
F
D
C
B
A
Transparent top view
Table 3. Pin allocation table
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Row A
1 P3[12]/D12 2 P3[2]/D2 3 P0[3]/RXD0 4 P3[9]/D9
5 P1[1]/ENET_TXD1 6 P3[8]/D8 7 P1[10]/ENET_RXD1 8 P1[15]/
ENET_REF_CLK/
ENET_RX_CLK
9 P1[3]/ENET_TXD3/
MCICMD/PWM0[2]
10 V
SSCORE
11 P0[4]/I2SRX_CLK/RD2/
CAP2[0]
12 P1[11]/ENET_RXD2/
MCIDAT2/PWM0[6]
13 P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
14 P1[12]/ENET_RXD3/
MCIDAT3/PCAP0[0]
15 - 16 -
Row B
1TDO 2P3[11]/D11 3P3[10]/D10 4V
SSIO
5 P1[0]/ENET_TXD0 6 P1[8]/ENET_CRS_DV/
ENET_CRS
7 P1[2]/ENET_TXD2/
MCICLK/PWM0[1]
8 P1[16]/ENET_MDC
9 P4[29]/
MAT2[1]/RXD3
10 P1[6]/ENET_TX_CLK/
MCIDAT0/PWM0[4]
11 P0[5]/I2SRX_WS/TD2/
CAP2[1]
12 P0[7]/I2STX_CLK/SCK1
/MAT2[1]
13 P1[5]/ENET_TX_ER/
MCIPWR/PWM0[3]
14 P4[13]/A13 15 - 16 -
Row C
1 P3[13]/D13 2 TMS 3 TDI 4 RTCK
5V
DD(3V3)
6 P1[4]/ENET_TX_EN 7 P4[30]/CS0 8 P4[24]/OE
9 P1[17]/ENET_MDIO 10 P4[15]/A15 11 V
SSIO
12 P0[8]/I2STX_WS/
MISO1/MAT2[2]
