xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC2458 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 15 October 2013 55 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
11.5 Static external memory interface
Table 15. Dynamic characteristics: Static external memory interface
C
L
=30pF, T
amb
=
40
C to 85
C, V
DD(DCDC)(3V3)
= V
DD(3V3)
= 3.0 V to 3.6 V
Symbol Parameter Conditions Min Typ Max Unit
Common to read and write cycles
[1]
t
CSLAV
CS LOW to address valid
time
0.29 0.20 2.54 ns
Read cycle parameters
[1][2]
t
OELAV
OE LOW to address valid
time
0.29 0.20 2.54 ns
t
CSLOEL
CS LOW to OE LOW time 0.78 + T
cy(CCLK)
WAITOEN 0 + T
cy(CCLK)
WAITOEN 0.49 + T
cy(CCLK)
WAITOEN ns
t
am
memory access time
[3][4]
(WAITRD WAITOEN + 1)
T
cy(CCLK)
12.70
(WAITRD WAITOEN + 1)
T
cy(CCLK)
9.57
(WAITRD WAITOEN + 1)
T
cy(CCLK)
8.11
ns
t
h(D)
data input hold time
[5]
0--ns
t
CSHOEH
CS HIGH to OE HIGH time 0.49 0 0.20 ns
t
OEHANV
OE HIGH to address invalid
time
0.20 0.20 2.44 ns
t
OELOEH
OE LOW to OE HIGH time 0.59 + (WAITRD
WAITOEN + 1) T
cy(CCLK)
0 + (WAITRD WAITOEN +
1) T
cy(CCLK)
0.10 + (WAITRD
WAITOEN + 1) T
cy(CCLK)
t
BLSLAV
BLS LOW to address valid
time
0.39 0 2.54 ns
t
CSHBLSH
CS HIGH to BLS HIGH time 0.88 0.49 0.68 ns
Write cycle parameters
[1][6]
t
CSLWEL
CS LOW to WE LOW time 0.88 + T
cy(CCLK)
(1 +
WAITWEN)
0.10 + T
cy(CCLK)
(1 +
WAITWEN)
0.20 + T
cy(CCLK)
(1 +
WAITWEN)
ns
t
CSLBLSL
CS LOW to BLS LOW time 0.88 0.49 0.98 ns
t
WELDV
WE LOW to data valid time 0.68 2.54 5.86 ns
t
CSLDV
CS LOW to data valid time 0 2.64 4.79 ns
t
WELWEH
WE LOW to WE HIGH time
[3]
0.78 + T
cy(CCLK)
(WAITWR WAITWEN + 1)
0 + T
cy(CCLK)
(WAITWR
WAITWEN + 1)
0.10 + T
cy(CCLK)
(WAITWR WAITWEN + 1)
ns
t
BLSLBLSH
BLS LOW to BLS HIGH
time
[3]
0.88 + T
cy(CCLK)
(WAITWR WAITWEN + 3)
0 + T
cy(CCLK)
(WAITWR
WAITWEN + 3)
0.59 + T
cy(CCLK)
(WAITWR WAITWEN + 3)
ns
t
WEHANV
WE HIGH to address invalid
time
[3]
0 + T
cy(CCLK)
0.20 + T
cy(CCLK)
2.74 + T
cy(CCLK)
ns
