LPC2458 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 15 October 2013 31 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
UART3 includes an IrDA mode to support infrared communication.
7.16 SPI serial I/O controller
The LPC2458 contains one SPI controller. SPI is a full duplex serial interface designed to
handle multiple masters and slaves connected to a given bus. Only a single master and a
single slave can communicate on the interface during a given data transfer. During a data
transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave
always sends 8 bits to 16 bits of data to the master.
7.16.1 Features
Compliant with SPI specification
Synchronous, Serial, Full Duplex Communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer
7.17 SSP serial I/O controller
The LPC2458 contains two SSP controllers. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the
bus. Only a single master and a single slave can communicate on the bus during a given
data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of
data flowing from the master to the slave and from the slave to the master. In practice,
often only one of these data flows carries meaningful data.
7.17.1 Features
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave
mode) of the input clock rate
DMA transfers supported by GPDMA
7.18 SD/MMC card interface
The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD
memory cards. The SD card interface conforms to the SD Multimedia Card Specification
Version 2.11.
7.18.1 Features
The MCI interface provides all functions specific to the SD/MMC memory card. These
include the clock generation unit, power management control, and command and data
transfer.
LPC2458 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 15 October 2013 32 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
Conforms to Multimedia Card Specification v2.11.
Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
Can be used as a multimedia card bus or a secure digital memory card bus host. The
SD/MMC can be connected to several multimedia cards or a single secure digital
memory card.
DMA supported through the GPDMA controller.
7.19 I
2
C-bus serial I/O controller
The LPC2458 contains three I
2
C-bus controllers.
The I
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus and can
be controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2458 supports bit rates up to 400 kbit/s (Fast I
2
C-bus).
7.19.1 Features
I
2
C0 is a standard I
2
C compliant bus interface with open-drain pins.
I
2
C1 and I
2
C2 use standard I/O pins and do not support powering off of individual
devices connected to the same bus lines.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus can be used for test and diagnostic purposes.
7.20 I
2
S-bus serial I/O controllers
The I
2
S-bus provides a standard communication interface for digital audio applications.
The I
2
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I
2
S connection has one master, which is always the
master, and one slave. The I
2
S interface on the LPC2458 provides a separate transmit
and receive channel, each of which can operate as either a master or a slave.
LPC2458 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4.1 — 15 October 2013 33 of 81
NXP Semiconductors
LPC2458
Single-chip 16-bit/32-bit micro
7.20.1 Features
The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
Configurable word select period in master mode (separately for I
2
S input and output).
Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop and mute options separately for I
2
S input and I
2
S output.
7.21 General purpose 32-bit timers/external event counters
The LPC2458 includes four 32-bit Timer/Counters. The Timer/Counter is designed to
count cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. The Timer/Counter also includes four capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
7.21.1 Features
A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Counter or Timer operation.
Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.

LPC2458FET180,551

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 512KF/USBH/ENET
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet