AD5371
Rev. B | Page 12 of 28
Pin No. Ball No. Mnemonic Description
58 D11 SIGGND0 Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
31 L7 SIGGND1 Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
41 L12 SIGGND2 Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
7 F1 SIGGND3 Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
16 L3 SIGGND4 Reference Ground for DAC 32 to DAC 39. VOUT32 to VOUT39 are referenced to this voltage.
52 G12 VREF0 Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
21 M4 VREF1 Reference Input for DAC 8 to DAC 15. This reference voltage is referred to AGND.
50 H11 VREF2 Reference Input for DAC 16 to DAC 39. This reference voltage is referred to AGND.
19, 44
J5 to J9, L11,
M12
V
DD
Positive Analog Power Supply; 9 V to 16.5 V for specified performance. Decouple these pins
with 0.1 μF ceramic capacitors and 10 μF capacitors.
20, 45
E4, F4, G4, H4,
J4, L2, M1
V
SS
Negative Analog Power Supply; −16.5 V to −8 V for specified performance. Decouple these
pins with 0.1 μF ceramic capacitors and 10 μF capacitors.
64, 76 A11, A12 DGND Ground for All Digital Circuitry. Connect both DGND pins to the DGND plane.
65, 75 A10, B10 DV
CC
Logic Power Supply; 2.5 V to 5.5 V. Decouple these pins with 0.1 μF ceramic capacitors and
10 μF capacitors.
66 A9
SYNC Active Low or Differential SYNC Input (Complement) for SPI or LVDS Interface. This is the
frame synchronization signal for the SPI or LVDS serial interface. See the Timing Characteristics
section for more details.
67 B9 SYNC
Differential SYNC Input for LVDS Interface. This is the frame synchronization signal for the
LVDS serial interface. See the
Timing Characteristics section for more details.
68 A8 SCLK
Serial Clock Input for SPI or LVDS Interface. See the
Timing Characteristics section for more
details.
69 B8
SCLK Differential Serial Clock Input (Complement) for LVDS Interface. See the Timing Characteristics
section for more details.
70 A7 SDI
Serial Data Input for SPI or LVDS Interface. See the
Timing Characteristics section for more
details.
71 B7
SDI Differential Serial Data Input (Complement) for LVDS Interface. See the Timing Characteristics
section for more details.
72 A6
SPI/LVDS Interface Selection Pin. If the pin is low, the SPI interface is selected. If the pin is high, the
LVDS interface is selected.
74 B5 SDO
Serial Data Output for SPI Interface. CMOS output. SDO can be used for readback. Data is
clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.
77
A1, B1, C1, C2,
D4 to D9, E9,
F9, G9, H9
AGND Ground for All Analog Circuitry. Connect the AGND pin to the AGND plane.
22 to 24,
35, 42,
43, 51,
53, 59
A2, B6, F2, F11,
G1, G11
NC No Connect. Do not connect these pins.
