AD5371
Rev. B | Page 6 of 28
TIMING CHARACTERISTICS
DV
CC
= 2.5 V to 5.5 V; V
DD
= 9 V to 16.5 V; V
SS
= −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; C
L
= 200 pF to GND;
R
L
= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4. SPI Interface
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit Description
t
1
20 ns min SCLK cycle time
t
2
8 ns min SCLK high time
t
3
8 ns min SCLK low time
t
4
11 ns min
SYNC falling edge to SCLK falling edge setup time
t
5
20 ns min
Minimum
SYNC high time
t
6
10 ns min
24
th
SCLK falling edge to SYNC rising edge
t
7
5 ns min Data setup time
t
8
5 ns min Data hold time
t
9
4
42 ns max
SYNC rising edge to BUSY falling edge
t
10
1/1.5 μs typ/μs max
BUSY pulse width low (single-channel update); see Table 9
t
11
600 ns max Single-channel update cycle time
t
12
20 ns min
SYNC rising edge to LDAC falling edge
t
13
10 ns min
LDAC pulse width low
t
14
3 μs max
BUSY rising edge to DAC output response time
t
15
0 ns min
BUSY rising edge to LDAC falling edge
t
16
3 μs max
LDAC falling edge to DAC output response time
t
17
20/30 μs typ/μs max DAC output settling time
t
18
140 ns max
CLR/RESET pulse activation time
t
19
30 ns min
RESET pulse width low
t
20
400 μs max
RESET time indicated by BUSY low
t
21
270 ns min
Minimum
SYNC high time in readback mode
t
22
5
25 ns max SCLK rising edge to SDO valid
t
23
80 ns max
RESET rising edge to BUSY falling edge
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 2 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
t
9
is measured with the load circuit shown in Figure 2.
5
t
22
is measured with the load circuit shown in Figure 3.
Table 5. LVDS Interface
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit Description
t
1
12 ns min SCLK cycle time
t
2
5 ns min SCLK pulse width high and low time
t
3
5 ns min
SYNC to SCLK setup time
t
4
3 ns min Data setup time
t
5
3 ns min Data hold time
t
6
3 ns min
SCLK to
SYNC hold time
t
7
10 ns min
SYNC high time
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 2 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 6.
