AD5371BBCZ-REEL Datasheet AD5371BBCZ, AD5371BBCZ-REEL, EVAL-AD5371EBZ | P19-P21

AD5371

Rev. B | Page 18 of 28

OUTPUT AMPLIFIER

The output amplifiers can swing to 1.4 V below the positive

supply and 1.4 V above the negative supply, which limits how

much the output can be offset for a given reference voltage. For

example, it is not possible to have a unipolar output range of

20 V, because the maximum supply voltage is ±16.5 V.

CLR

DAC

CHANNEL

OFFSET

DAC

OUT

10kΩ

20kΩ

60kΩ

20kΩ

SIGGNDx

60kΩ

20kΩ

05814-022

Figure 22. Output Amplifier and Offset DAC

Figure 22 shows details of a DAC output amplifier and its

connections to its corresponding offset DAC. On power-up,

S1 is open, disconnecting the amplifier from the output. S3 is

closed, so the output is pulled to the corresponding SIGGNDx

(R1 and R2 are greater than R6). S2 is also closed to prevent the

output amplifier from being open-loop. If

CLR

is low at power-up,

the output remains in this condition until

CLR

is taken high.

The DAC registers can be programmed, and the outputs assume

the programmed values when

CLR

is taken high. Even if

CLR

high at power-up, the output remains in this condition until

> 6 V and V

< −4 V and the initialization sequence has

finished. The outputs then go to their power-on default value.

TRANSFER FUNCTION

DAC CODE

FULL-SCALE

ERROR

ZERO-SCALE

ERROR

ZERO-SCALE

ERROR

–4V

16383

IDEAL

TRANSFER

FUNCTION

ACTUAL

TRANSFER

FUNCTION

OUTPUT

VOLTAGE

05814-008

Figure 23. DAC Transfer Function

The output voltage of a DAC in the AD5371 is dependent on the

value in the input register, the value of the M and C registers,

and the value in the offset DAC.

The input code is the value in the X1A or X1B register that is

applied to the DAC (X1A, X1B default code = 5461).

DAC_CODE = INPUT_CODE × (M + 1)/2

+ C − 2

where:

M = code in gain register − default code = 2

− 1.

C = code in offset register − default code = 2

The DAC output voltage is calculated as follows:

VOUT = 4 × VREFx × (DAC_CODE –

OFFSET_CODE)/2

+ V

SIGGND

where:

DAC_CODE should be within the range of 0 to 16,383.

VREF = 3.0 V for a 12 V span and 5.0 V for a 20 V span.

OFFSET_CODE is the code loaded to the offset DAC. On

power-up, the default code loaded to the offset DAC is 5461

(0x1555). With a 3 V reference, this gives a span of −4 V to +8 V.

REFERENCE SELECTION

The AD5371 has three reference input pins. The voltage applied

to the reference pins determines the output voltage span on

VOUT0 to VOUT39. VREF0 determines the voltage span for

VOUT0 to VOUT7 (Group 0), VREF1 determines the voltage

span for VOUT8 to VOUT15 (Group 1), and VREF2 deter-

mines the voltage span for VOUT16 to VOUT39 (Group 2 to

Group 4). The reference voltage applied to each VREF pin can

be different, if required, allowing each group to have a different

voltage span. The output voltage range and span can be adjusted

further by programming the offset and gain registers for each

channel and by programming the offset DACs. If the offset and

gain features are not used (that is, the M and C registers are left

at their default values), the required reference levels can be

calculated as follows:

VREF = (VOUT

MAX

− VOUT

MIN

)/4

If the offset and gain features of the AD5371 are used, the

required output range is slightly different. The selected output

range should take into account the system offset and gain errors

that need to be trimmed out. Therefore, the selected output

range should be larger than the actual required range.

Calculate the required reference levels as follows:

1. Identify the nominal output range on VOUT.

2. Identify the maximum offset span and the maximum gain

required on the full output signal range.

3. Calculate the new maximum output range on VOUT,

including the expected maximum offset and gain errors.

4. Choose the new required VOUT

MAX

and VOUT

MIN

, keeping

the VOUT limits centered on the nominal values. Note that

and V

must provide sufficient headroom.

5. Calculate the value of VREF as follows:

VREF = (VOUT

MAX

− VOUT

MIN

)/4

AD5371

Rev. B | Page 19 of 28

Reference Selection Example

Nominal output range = 12 V (−4 V to +8 V)

Zero-scale error = ±70 mV

Gain error = ±3%, and

SIGGNDx = AGND = 0 V

Then

Gain error = ±3%

=> Maximum positive gain error = 3%

=> Output range including gain error = 12 + 0.03(12) = 12.36 V

Zero-scale error = ±70 mV

=> Maximum offset error span = 2(70 mV) = 0.14 V

=> Output range including gain error and zero-scale error =

12.36 V + 0.14 V = 12.5 V

VREF calculation

Actual output range = 12.5 V, that is, −4.25 V to +8.25 V;

VREF = (8.25 V + 4.25 V)/4 = 3.125 V

If the solution yields an inconvenient reference level, the user

can adopt one of the following approaches:

• Use a resistor divider to divide down a convenient, higher

reference level to the required level.

• Select a convenient reference level above VREF and modify

the gain and offset registers to digitally downsize the reference.

In this way, the user can use almost any convenient reference

level but can reduce the performance by overcompaction of

the transfer function.

• Use a combination of these two approaches.

CALIBRATION

The user can perform a system calibration on the AD5371 to

reduce gain and offset errors to below 1 LSB. This reduction is

achieved by calculating new values for the M and C registers and

reprogramming them.

The M and C registers should not be programmed until both

the zero-scale and full-scale errors are calculated.

Reducing Zero-Scale Error

Zero-scale error can be reduced as follows:

1. Set the output to the lowest possible value.

2. Measure the actual output voltage and compare it to the

required value. This gives the zero-scale error.

3. Calculate the number of LSBs equivalent to the error and

add this number to the default value of the C register. Note

that only negative zero-scale error can be reduced.

Reducing Full-Scale Error

Full-scale error can be reduced as follows:

1. Measure the zero-scale error.

2. Set the output to the highest possible value.

3. Measure the actual output voltage and compare it to the

required value. Add this error to the zero-scale error. This

is the span error, which includes the full-scale error.

4. Calculate the number of LSBs equivalent to the span error

and subtract this number from the default value of the M

reduced.

AD5371 Calibration Example

This example assumes that a −4 V to +8 V output is required.

The DAC output is set to −4 V but measured at −4.03 V. This

gives a zero-scale error of −30 mV.

1 LSB = 12 V/16,384 = 732.42 μV

30 mV = 41 LSBs

The full-scale error can now be calculated. The output is set to

8 V and a value of 8.02 V is measured. This gives a full-scale

error of +20 mV and a span error of +20 mV − (−30 mV) =

+50 mV.

50 mV = 68 LSBs

The errors can now be removed as follows:

1. Add 41 LSBs to the default C register value:

8192 + 41 = 8233

2. Subtract 68 LSBs from the default M register value:

16,383 − 68 = 16,315

3. Program the M register to 16,315; program the C register

to 8233.

ADDITIONAL CALIBRATION

The techniques described in the previous section are usually

enough to reduce the zero-scale and full-scale errors in most

applications. However, there are limitations whereby the errors

may not be sufficiently reduced. For example, the offset (C)

negative zero-scale error. A positive offset cannot be reduced.

Likewise, if the maximum voltage is below the ideal value, that

is, a negative full-scale error, the gain (M) register cannot be

used to increase the gain to compensate for the error.

These limitations can be overcome by increasing the reference

value. With a 3 V reference, a 12 V span is achieved. The ideal

voltage range for the AD5371 is −4 V to +8 V. Using a +3.1 V

reference increases the range to −4.133 V to +8.2667 V. Clearly,

in this case, the offset and gain errors are insignificant, and the

M and C registers can be used to raise the negative voltage to

−4 V and then reduce the maximum voltage to +8 V to give the

most accurate values possible.

AD5371

Rev. B | Page 20 of 28

RESET FUNCTION

The reset function is initiated by the

RESET

pin. On the rising

edge of

RESET

, the AD5371 state machine initiates a reset

sequence to reset the X, M, and C registers to their default values.

This sequence typically takes 300 μs, and the user should not

write to the part during this time. On power-up, it is recom-

mended that the user bring

RESET

high as soon as possible to

properly initialize the registers.

When the reset sequence is complete (and provided that

CLR

high), the DAC output is at a potential specified by the default

outputs remain at SIGGNDx until the X, M, or C register is

updated and

LDAC

is taken low. The AD5371 can be returned

to the default state by pulsing

RESET

low for at least 30 ns. Note

that, because the reset function is triggered by the rising edge,

bringing

RESET

low has no effect on the operation of the AD5371.

CLEAR FUNCTION

CLR

is an active low input that should be high for normal oper-

ation. The

CLR

pin has an internal 500 kΩ pull-down resistor.

When

CLR

is low, the input to each of the DAC output buffer

stages, VOUT0 to VOUT39, is switched to the externally set

potential on the relevant SIGGNDx pin. While

CLR

is low, all

LDAC

pulses are ignored. When

CLR

is taken high again, the

DAC outputs return to their previous values. The contents of

the input registers and the DAC registers are not affected by

taking

CLR

low. To prevent glitches from appearing on the

outputs, bring

CLR

low before writing to the offset DAC to

adjust the output span.

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the

user writes new data to the corresponding X1, C, or M register.

During the calculation of X2, the

BUSY

output goes low. While

BUSY

is low, the user can continue writing new data to the X1,

M, or C register (see the

details), but no DAC output updates can take place.

The

BUSY

pin is bidirectional and has a 50 kΩ internal pull-up

resistor. When multiple AD5371 devices are used in one system,

the

BUSY

pins can be tied together. This is useful when it is

required that no DAC in any device be updated until all other

DACs are ready to be updated. When each device has finished

updating the X2 (A or B) register, it releases the

BUSY

pin. If

another device has not finished updating its X2 register, it holds

BUSY

low, thus delaying the effect of

LDAC

going low.

The DAC outputs are updated by taking the

LDAC

input low. If

LDAC

goes low while

BUSY

is active, the

LDAC

event is stored

and the DAC outputs are updated immediately after

BUSY

goes

high. A user can also hold the

LDAC

input permanently low.

In this case, the DAC outputs are updated immediately after

BUSY

goes high. Whenever the A/B select registers are written

to,

BUSY

also goes low for approximately 500 ns.

The AD5371 has flexible addressing that allows writing of data

to a single channel, all channels in a group, the same channel in

Group 0 to Group 4, the same channel in Group 1 to Group 4, or

all channels in the device. This means that 1, 4, 5, 8, or 40 DAC

there is only one multiplier shared among 40 channels, this task

must be done sequentially so that the length of the

BUSY

pulse

varies according to the number of channels being updated.

Table 9.

BUSY

Pulse Widths

Action

BUSY

Pulse Width

Loading X1A, X1B, C, or M to 1 channel

1.5 μs maximum

Loading X1A, X1B, C, or M to 5 channels 3.9 μs maximum

Loading X1A, X1B, C, or M to 8 channels 5.7 μs maximum

Loading X1A, X1B, C, or M to 40 channels 24.9 μs maximum

BUSY

pulse width = ((number of channels + 1) × 600 ns) + 300 ns.

A single channel update is typically 1 μs.

The AD5371 contains an extra feature whereby a DAC register

is not updated unless its X2A or X2B register has been written

to since the last time

LDAC

was brought low. Normally, when

LDAC

is brought low, the DAC registers are filled with the contents

of the X2A or X2B register, depending on the setting of the A/B

select registers. However, the AD5371 updates the DAC register

only if the X2A or X2B data has changed, thereby removing

unnecessary digital crosstalk.

POWER-DOWN MODE

The AD5371 can be powered down by setting Bit 0 in the

control register to 1. This turns off the DACs, thus reducing the

current consumption. The DAC outputs are connected to their

respective SIGGNDx potentials. The power-down mode does

not change the contents of the registers, and the DACs return to

their previous voltage when the power-down bit is cleared to 0.

THERMAL SHUTDOWN FUNCTION

The AD5371 can be programmed to shut down the DACs if

the temperature on the die exceeds 130°C. Setting Bit 1 in the

control register to 1 enables this function (see

Table 17). If the

die temperature exceeds 130°C, the AD5371 enters a thermal

shutdown mode that is equivalent to setting the power-down bit

in the control register to 1. To indicate that the AD5371 has

entered thermal shutdown mode, Bit 4 of the control register is

set to 1. The AD5371 remains in thermal shutdown mode, even

if the die temperature falls, until Bit 1 in the control register is

cleared to 0.

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AD5371BBCZ-REEL

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 40-CH 14-bit Serial bipolar IC

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AD5371BBCZ-REEL

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