AD5371
Rev. B | Page 23 of 28
SPI READBACK MODE
The AD5371 allows data readback via the serial interface from
every register directly accessible to the serial interface, that is,
all registers except the X2A, X2B, and DAC data registers. To
read back a register, it is first necessary to tell the AD5371
which register is to be read. This is achieved by writing a word
whose first two bits are the Special Function Code 00 to the
device. The remaining bits then determine which register is to
be read back.
If a readback command is written to a special function register,
data from the selected register is clocked out of the SDO pin
during the next SPI operation. The SDO pin is normally three-
stated but becomes driven as soon as a read command is issued.
The pin remains driven until the register data is clocked out.
See
Figure 5 for the read timing diagram. Note that due to the
timing requirements of t
22
(25 ns), the maximum speed of the
SPI interface during a read operation should not exceed 20 MHz.
LVDS OPERATION
The LVDS interface operates as follows. Note that, because the
LVDS signals are differential, when a signal goes high, its
complementary signal goes low, and vice versa.
1. The
SYNC
signal frames the data. SCLK is initially high.
2. After
SYNC
goes high and the
SYNC
-to-SCLK setup time
has elapsed, SCLK can start to clock in the data.
3. Data is clocked into the AD5371 on the high-to-low
transition of SCLK and must be stable at this time (observe
setup and hold time specifications).
4.
SYNC
can then be taken low after the SCLK-to-
SYNC
hold
time to latch the data.
The same comments about burst and continuous clocks for the
SPI interface apply to the LVDS interface. However, readback is
not available when using the LVDS interface.
REGISTER UPDATE RATES
The value of the X2A register or the X2B register is calculated
each time the user writes new data to the corresponding X1, C, or
M register. The calculation is performed by a three-stage process.
The first two stages take approximately 600 ns each, and the
third stage takes approximately 300 ns. When the write to the
X1, C, or M register is complete, the calculation process begins.
If the write operation involves the update of a single DAC channel,
the user is free to write to another register, provided that the
write operation does not finish until the first-stage calculation is
complete, that is, 600 ns after the completion of the first write
operation. If a group of channels is being updated by a single
write operation, the first-stage calculation is repeated for each
channel, taking 600 ns per channel. In this case, the user should
not complete the next write operation until this time has elapsed.
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, the data-word D13 to D0 is written
to the device. Address Bit A5 to Address Bit A0 determine
which channels are written to, and the mode bits determine to
which register (X1A, X1B, C, or M) the data is written, as shown in
Table 14 and Table 15. Data is to be written to the X1A register
when the
A
/B bit in the control register is 0, or to the X1B
register when the
A
/B bit is 1.
Table 14. Mode Bits
M1 M0 Action
1 1 Write to DAC input data (X) register
1 0 Write to DAC offset (C) register
0 1 Write to DAC gain (M) register
0 0
Special function, used in combination
with other bits of the data-word
The AD5371 has very flexible addressing that allows the writing
of data to a single channel, all channels in a group, the same
channel in Group 0 to Group 4, the same channel in Group 1 to
Group 4, or all channels in the device (see
Table 15).
