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AD5371BBCZ-REEL

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AD5371
Rev. B | Page 3 of 28
GENERAL DESCRIPTION
The AD5371
1
contains 40 14-bit DACs in a single 80-lead LQFP
or 100-ball CSP_BGA. The device provides buffered voltage
outputs with a span of 4× the reference voltage. The gain and
offset of each DAC can be independently trimmed to remove
errors. For even greater flexibility, the device is divided into five
groups of eight DACs. Three offset DACs allow the output range
of the groups to be adjusted. Group 0 can be adjusted by Offset
DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2
to Group 4 can be adjusted by Offset DAC 2.
The AD5371 offers guaranteed operation over a wide supply
range, with V
SS
from −16.5 V to −4.5 V and V
DD
from 9 V to
16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
The AD5371 has a high speed serial interface that is compatible
with SPI, QSPI™, MICROWIRE™, and DSP interface standards
and can handle clock speeds of up to 50 MHz. It also has a
100 MHz low voltage differential signaling (LVDS) serial
interface.
The DAC registers are updated on reception of new data. All the
outputs can be updated simultaneously by taking the
LDAC
input low. Each channel has a programmable gain and an offset
adjust register to allow removal of gain and offset errors.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the
CLR
pin.
Table 1. High Channel Count Bipolar DACs
Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB)
AD5360 16 4 × V
REF
(20 V) 16 ±4
AD5361 14 4 × V
REF
(20 V) 16 ±1
AD5362 16 4 × V
REF
(20 V) 8 ±4
AD5363 14 4 × V
REF
(20 V) 8 ±1
AD5370 16 4 × V
REF
(12 V) 40 ±4
AD5371 14 4 × V
REF
(12 V) 40 ±1
AD5372 16 4 × V
REF
(12 V) 32 ±4
AD5373 14 4 × V
REF
(12 V) 32 ±1
AD5378 14 ±8.75 V 32 ±3
AD5379 14 ±8.75 V 40 ±3
AD5371
Rev. B | Page 4 of 28
SPECIFICATIONS
PERFORMANCE SPECIFICATIONS
DV
CC
= 2.5 V to 5.5 V; V
DD
= 9 V to 16.5 V; V
SS
= −16.5 V to −8 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; C
L
= open circuit;
R
L
= open circuit; gain (M), offset (C), and DAC offset registers at default values; temperature range for the AD5371 is −40°C to +85°C; all
specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter Min Typ
1
Max Unit Test Conditions/Comments
1
ACCURACY
Resolution 14 Bits
Integral Nonlinearity (INL) −1 +1 LSB
Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic by design
Zero-Scale Error −10 +10 mV Before calibration
Full-Scale Error −10 +10 mV Before calibration
Gain Error 0.1 % FSR
Zero-Scale Error
2
1 LSB After calibration
Full-Scale Error
2
1 LSB After calibration
Span Error of Offset DAC −35 +35 mV See the Offset DACs section for details
VOUTx Temperature Coefficient
(VOUT0 to VOUT39)
5
ppm
FSR/°C
Includes linearity, offset, and gain drift
DC Crosstalk
2
120 µV
Typically 20 µV; measured channel at midscale,
full-scale change on any other channel
REFERENCE INPUTS (VREF0, VREF1, VREF2)
2
VREFx Input Current −10 +10 µA Per input; typically ±30 nA
VREFx Range 2 5 V ±2% for specified operation
SIGGND INPUTS (SIGGND0 TO SIGGND4)
2
DC Input Impedance 50 kΩ Typically 55 kΩ
Input Range −0.5 +0.5 V
SIGGNDx Gain 0.995 1.005
OUTPUT CHARACTERISTICS
2
Output Voltage Range V
SS
+ 1.4 V
DD
− 1.4 V I
LOAD
= 1 mA
Nominal Output Voltage Range −4 +8 V
Short-Circuit Current 15 mA VOUTx to DV
CC
, V
DD
, or V
SS
Load Current −1 +1 mA
Capacitive Load 2200 pF
DC Output Impedance 0.5 Ω
DIGITAL INPUTS
Input High Voltage 1.7 V DV
CC
= 2.5 V to 3.6 V
2.0 V DV
CC
= 3.6 V to 5.5 V
Input Low Voltage 0.8 V DV
CC
= 2.5 V to 5.5 V
Input Current −1 +1 µA
Excluding CLR
pin
CLR High Impedance Leakage Current
−20 +20 µA
Input Capacitance
2
10 pF
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage 0.5 V Sinking 200 A
Output High Voltage (SDO) DV
CC
− 0.5 V Sourcing 200 A
SDO High Impedance Leakage Current −5 +5 µA
High Impedance Output Capacitance
2
10 pF
AD5371
Rev. B | Page 5 of 28
Parameter Min Typ
1
Max Unit Test Conditions/Comments
1
LVDS INTERFACE (REDUCED RANGE LINK)
Digital Inputs
2
Input Voltage Range 875 1575 mV
Input Differential Threshold –0.1 +0.1 V
External Termination Resistance 80 100 132 Ω
Differential Input Voltage 100 mV
POWER REQUIREMENTS
DV
CC
2.5 5.5 V
V
DD
9 16.5 V
V
SS
−16.5 −4.5 V
Power Supply Sensitivity
2
∆Full Scale/∆V
DD
−75 dB
∆Full Scale/∆V
SS
−75 dB
∆Full Scale/∆DV
CC
−90 dB
DI
CC
2 mA
DV
CC
= 5.5 V, V
IH
= DV
CC
, V
IL
= GND; normal
operating conditions
I
DD
18 mA Outputs unloaded, DAC outputs = 0 V
20 mA Outputs unloaded, DAC outputs = full scale
I
SS
−18 mA Outputs unloaded, DAC outputs = 0 V
−20 mA Outputs unloaded, DAC outputs = full scale
Power Dissipation Unloaded (P) 280 mW V
SS
= −8 V, V
DD
= 9.5 V, DV
CC
= 2.5 V
Power-Down Mode Control register power-down bit set
DI
CC
5 μA
I
DD
35 μA
I
SS
−35 μA
Junction Temperature
3
130 °C T
J
= T
A
+ P
TOTAL
× θ
JA
1
Typical specifications are at 25°C.
2
Guaranteed by design and characterization; not production tested.
3
θ
JA
represents the package thermal impedance.
AC CHARACTERISTICS
DV
CC
= 2.5 V; V
DD
= 15 V; V
SS
= −15 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; C
L
= 200 pF; R
L
= 10 kΩ; gain (M), offset (C),
and DAC offset registers at default values; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3. AC Characteristics
1
Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 20 μs Settling to 1 LSB from a full-scale change
30 μs DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate 1 V/μs
Digital-to-Analog Glitch Energy 5 nV-s
Glitch Impulse Peak Amplitude 10 mV
Channel-to-Channel Isolation 100 dB VREF0, VREF1, VREF2 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk 20 nV-s
Digital Crosstalk 0.2 nV-s
Digital Feedthrough 0.02 nV-s Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz 250 nV/√Hz V
REF
= 0 V
1
Guaranteed by design and characterization; not production tested.
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AD5371BBCZ-REEL

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Buy AD5371BBCZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 40-CH 14-bit Serial bipolar IC
Lifecycle:
New from this manufacturer.
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