28
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
06/02/08
IS42S32200E
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
WRITE
NOP NOP NOP NOP ACTIVE
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
tWR
tRP
PRECHARGE
DIN n
DIN n+1
WRITE to PRECHARGE (tWR = 2 CLK (tWR > tCK)
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2
WRITE
D
IN
n
(DATA)
BANK,
COL n
DON'T CARE
(ADDRESS)
BURST
TERMINATE
NEXT
COMMAND
WRITE Burst Termination
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
29
Rev. 00D
06/02/08
IS42S32200E
CLK
CKE
HIGH - Z
ALL BANKS
BANK SELECT
BANK ADDRESS
CS
RAS
CAS
WE
A0-A9
A10
BA0, BA1
DON'T CARE
CLK
CKE
COMMAND
NOP NOP
ACTIVE
t
CKStCKS
All banks idle
Enter
power-down mode
Exit power-down mode
tRCD
tRAS
tRC
Input buffers gated
off
PRECHARGE Command
POWER-DOWN
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses are
in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-
down occurs when there is a row active in either bank, this
mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding
CKE, for maximum power savings while in standby. The
device may not remain in the power-down state longer than
the refresh period (64ms) since no refresh operations are
performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tCKS). See figure below.
PRECHARGE
The PRECHARGE command (see figure) is used to
deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a
subsequent row access some specified time (t
RP) after
the PRECHARGE command is issued. Input A10 deter-
mines whether one or all banks are to be precharged, and
in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE com-
mands being issued to that bank.
30
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
06/02/08
IS42S32200E
DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
NOP
WRITE
NOP NOP
BANK a,
COL n
D
IN
n
D
IN
n+1 D
IN
n+2
INTERNAL
CLOCK
DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ
NOP NOP NOP NOP NOP
BANK a,
COL n
D
OUT
n
DOUT n+1
D
OUT
n+2
D
OUT
n+3
INTERNAL
CLOCK
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Burst Length 4 or greater DQM is low.
CAS Latency=2. Burst Length =4 or greater. DQM is low.

IS42S32200E-6BI-TR

Mfr. #:
Manufacturer:
Description:
DRAM 64M (2Mx32) 166MHz SDRAM, 3.3v
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