Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
37
Rev. 00D
06/02/08
IS42S32200E
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
(1)
SYMBOL PARAMETER CONDITION -5 -6 -7 UNITS
Clock Cycle Time 5 6 7 ns
Operating Frequency CL=3 200 166 143 MHz
tCCD READ/WRITE command to READ/WRITE command 1 1 1 cycle
tCKED CKE to clock disable or power-down entry mode 1 1 1 cycle
tPED CKE to clock enable or power-down exit setup mode 1 1 1 cycle
tDQD DQM to input data delay 0 0 0 cycle
tDQM DQM to data mask during WRITEs 0 0 0 cycle
tDQZ DQM to data high-impedance during READs 2 2 2 cycle
tDWD WRITE command to input data delay 0 0 0 cycle
tDAL Data-in to ACTIVE command CL=3 5 5 5 cycle
CL=2 4 4 4
tDPL Data-in to PRECHARGE command 2 2 2 cycle
tBDL Last data-in to burst STOP command 1 1 1 cycle
tCDL Last data-in to new READ/WRITE command 1 1 1 cycle
tRDL Last data-in to PRECHARGE command 2 2 2 cycle
tMRD LOAD MODE REGISTER command 2 2 2 cycle
to ACTIVE or REFRESH command
tROH Data-out to high-impedance from CL = 3 3 3 3 cycle
PRECHARGE command CL = 2 2 2 2
Note:
1. If CL = 2, the minimum t
CK2 is 10ns.
AC TEST CONDITIONS (Input/Output Reference Level: 1.5V)
Input Load
Output Load
2.75V
1.5V
0.25V
CLK
INPUT
OUTPUT
t
CHI
tCH
tAC
tOH
tCS
tCK
tCL
2.75V
1.5V
1.5V 1.5V
0.25V
I/O
50 Ω
+1.5V
30 pF
38
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
06/02/08
IS42S32200E
INITIALIZE AND LOAD MODE REGISTER
DON'T CARE
CLK
CKE
COMMAND
DQM0-DQM3
A0-A9
A10
BA0, BA1
DQ
t
CH
t
CL
t
CK
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CKS
t
CKH
T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3
t
MRD
t
RFC
t
RFC
t
RP
ROW
ROW
BANK
t
AS
t
AH
t
AS
t
AH
CODE
CODE
ALL BANKS
SINGLE BANK
ALL BANKS
AUTO
REFRESH
AUTO
REFRESH
Load MODE
REGISTER
T = 100µs Min.
Power-up: V
CC
and CLK stable
Precharge
all banks
AUTO REFRESH AUTO REFRESH Program MODE REGISTER
NOP
PRECHARGE
NOP NOP NOP ACTIVE
T
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
39
Rev. 00D
06/02/08
IS42S32200E
POWER-DOWN MODE CYCLE
CAS latency = 2, 3
DON'T CARE
CLK
CKE
COMMAND
DQM0-DQM3
A0-A9
A10
BA0, BA1
DQ
tAS tAH
BANK
tCH
tCLtCK
tCMS tCMH
tCKS tCKH
PRECHARGE
NOP NOP NOP
ACTIVE
ALL BANKS
SINGLE BANK
ROW
ROW
BANK
t
CKStCKS
Precharge all
active banks
All banks idle
Two clock cycles
Input buffers gated
off while in
power-down mode
All banks idle, enter
power-down mode
Exit
p
ower-down mode
T0 T1 T2 Tn+1 Tn+2
High-Z

IS42S32200E-6BI-TR

Mfr. #:
Manufacturer:
Description:
DRAM 64M (2Mx32) 166MHz SDRAM, 3.3v
Lifecycle:
New from this manufacturer.
Delivery:
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