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IS42S32200E-6BI-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
31
Rev. 00D
06/02/08
IS42S32200E
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DOUT a
DOUT a+1
DOUT b
DOUT b+1
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
t
RP - BANK n
t
RP - BANK m
READ - AP
BANK n
READ - AP
BANK m
Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active READ with Burst of 4 Precharge
Internal States
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DOUT a
DIN b
DIN b+1
DIN b+2
DIN b+3
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK n)
t
RP - BANK n
t
RP - BANK m
Read - AP
BANK n
WRITE - AP
BANK m
READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active WRITE with Burst of 4 Write-Back
Internal States
Page Active
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit
(M9)
in the mode register to a logic 1.
In this mode, all
WRITE
commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a READ on bank n, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
2. Interrupted by a WRITE (with or without auto precharge):
A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
32
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
06/02/08
IS42S32200E
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
D
IN
a
D
IN
a+1
D
OUT
b
D
OUT
b+1
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK m)
t
RP - BANK n
t
RP - BANK m
WRITE - AP
BANK n
READ - AP
BANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active READ with Burst of 4 Precharge
Internal States
t
WR
- BANK n
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
BANK n,
COL a
BANK m,
COL b
t
RP - BANK n
t
RP - BANK m
WRITE - AP
BANK n
WRITE - AP
BANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active WRITE with Burst of 4 Write-Back
Internal States
t
WR
- BANK n
D
IN
a
D
IN
a+1 D
IN
a+2
D
IN
b
D
IN
b+1 D
IN
b+2 D
IN
b+3
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing
CAS latency
later.
The PRECHARGE to bank n will begin after tWR is met,
where t
WR begins when the READ to bank m is registered.
The last valid
WRITE
to bank n will be data-in registered
one clock prior to the READ to bank m.
4. Interrupted by a WRITE (with or without auto precharge):
A
WRITE
to bank m will interrupt a
WRITE
on bank n when
registered. The PRECHARGE to bank n will begin after
tWR is met, where tWR begins when the WRITE to bank
m is registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
33
Rev. 00D
06/02/08
IS42S32200E
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameters Rating Unit
VDD MAX Maximum Supply Voltage –1.0 to +4.6 V
VDDQ
MAX Maximum Supply Voltage for Output Buffer –1.0 to +4.6 V
VIN Input Voltage –1.0 to +4.6 V
VOUT Output Voltage –1.0 to +4.6 V
PD MAX Allowable Power Dissipation 1 W
ICS Output Shorted Current 50 mA
T
OPR Operating Temperature Com. 0 to +70 °C
Ind. –40 to +85
TSTG Storage Temperature –55 to +150 °C
DC RECOMMENDED OPERATING CONDITIONS
(2,5)
(TA = -40 to +85°C for Industrial, TA = 0 to +70°C for Commercial)
Symbol Parameter Min. Typ. Max. Unit
VDD, VDDQ Supply Voltage (-5) 3.15 3.3 3.45 V
VDD, VDDQ Supply Voltage (-6, -7) 3.0 3.3 3.6 V
VIH Input High Voltage
(3)
2.0 — VDD + 0.3 V
VIL Input Low Voltage
(4)
-0.3 — +0.8 V
CAPACITANCE CHARACTERISTICS
(1,2)
(At TA = 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V, f = 1 MHz)
Symbol Parameter Typ. Max. Unit
CIN1 Input Capacitance: A0-A10, BA0, BA1 — 4 pF
CIN2 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) — 4 pF
CI/O Data Input/Output Capacitance: DQ0-DQ31 — 5 pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. All voltages are referenced to GND.
3. V
IH (max) = VDDQ + 2.0V with a pulse width ≤ 3 ns. The pluse width cannot be greater than one third of the cycle rate.
4. V
IL (min) = GND – 2.0V with a pulse < 3 ns. The pluse width cannot be greater than one third of the cycle rate.
5. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device operation
is ensured. (Vdd and VddQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated anytime the t
REF refresh requirement is exceeded.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P59

IS42S32200E-6BI-TR

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Description:
DRAM 64M (2Mx32) 166MHz SDRAM, 3.3v
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