34
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
06/02/08
IS42S32200E
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current 0V V IN V DD, with pins other than 5 5 µA
the tested pin at 0V
IOL Output Leakage Current Output is disabled, 0V V OUT V DD –5 5 µA
VOH Output High Voltage Level IOUT = –2 mA 2.4 V
VOL Output Low Voltage Level IOUT = +2 mA 0.4 V
ICC1 Operating Current
(1,2)
One Bank Operation, CAS latency = 3 Com. -5 130 mA
Burst Length=1 Com. -6 95 mA
tRC t RC (min.) Com. -7 85 mA
IOUT = 0mA Ind. -7 145 mA
ICC2P Precharge Standby Current CKE VIL ( MAX)tCK = 15ns Com. 2 mA
Ind. 4 mA
ICC2PS (In Power-Down Mode) tCK = Com. 1 mA
Ind. 3 mA
ICC3P Active Standby Current CKE V IL ( MAX)tCK = 10ns Com. 7 mA
Ind. 7 mA
ICC3PS (In Power-Down Mode) tCK = Com. 5 mA
Ind. 5 mA
ICC4 Operating Current tCK = tCK (MIN) CAS latency = 3 Com. -5 180 mA
(In Burst Mode)
(1)
IOUT = 0mA Com. -6 130 mA
BL = 4; 4 banks activated Com. -7 100 mA
Ind. -7 110 mA
ICC5 Auto-Refresh Current tRC = tRC (MIN) CAS latency = 3 Com. -5 150 mA
tCLK = tCLK ( MIN) Com. -6 150 mA
Com. -7 130 mA
Ind. -7 150 mA
ICC6 Self-Refresh Current CKE 0.2V 1 mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between V
DD and GND for each memory
chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc
1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
35
Rev. 00D
06/02/08
IS42S32200E
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-5 -6 -7
Symbol Parameter Condition Min. Max. Min. Max. Min. Max. Units
tCK3 Clock Cycle Time CAS Latency = 3 5 6 7 ns
tCK2 CAS Latency = 2 10 10 10 ns
tAC3 Access Time From CLK
(4)
CAS Latency = 3 4.5 5.5 5.5 ns
tAC2 CAS Latency = 2 7.5 7.5 8 ns
tCH CLK HIGH Level Width 2 2 2.5 ns
tCL CLK LOW Level Width 2 2 2.5 ns
tOH Output Data Hold Time 2 2 2.5 ns
tLZ Output LOW Impedance Time 0 0 0 ns
tHZ3 Output HIGH Impedance Time
(5)
CAS Latency = 3 4.5 5.5 5.5 ns
tHZ2 CAS Latency = 2 7.5 7.5 8 ns
tDS Input Data Setup Time 1.5 1.5 1.5 ns
tDH Input Data Hold Time 0.8 0.8 0.8 ns
tAS Address Setup Time 1.5 1.5 1.5 ns
tAH Address Hold Time 0.8 0.8 0.8 ns
tCKS CKE Setup Time 1 1 1 ns
tCKH CKE Hold Time 0.8 0.8 0.8 ns
tCKA CKE to CLK Recovery Delay Time
1CLK+3
1CLK+3
1CLK+3
—ns
tCS Command Setup Time (CS, RAS, CAS, WE, DQM) 1.5 1.5 2 ns
tCH Command Hold Time (CS, RAS, CAS, WE, DQM) 0.8 0.8 1 ns
tRC Command Period (REF to REF / ACT to ACT) 55 60 63 ns
tRAS Command Period (ACT to PRE) 38.7 120K 38.7
120K
38.7
120K
ns
tRP Command Period (PRE to ACT) 15 18 20 ns
tRCD Active Command To Read / Write Command Delay Time 15 18 20 ns
tRRD Command Period (ACT [0] to ACT[1]) 10 12 14 ns
36
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00D
06/02/08
IS42S32200E
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-5 -6 -7
Symbol Parameter Condition Min. Max. Min. Max. Min. Max. Units
t
DPL3 Input Data To Precharge CAS Latency = 3 2CLK 2CLK 2CLK ns
Command Delay time
tDPL2 CAS Latency = 2 2CLK 2CLK 2CLK ns
t
DAL3 Input Data To Active / Refresh CAS Latency = 3
2CLK+tRP
2CLK+tRP
2CLK+tRP
—ns
Command Delay time (During Auto-Precharge)
tDAL2 CAS Latency = 2
2CLK+tRP
2CLK+tRP
2CLK+tRP
—ns
tT Transition Time
(2)
0.3 1.2 0.3 1.2 0.3 1.2 ns
tWR Write Recovery Time
1CLK+5ns
1CLK+6ns
1CLK+7ns
—tCK
tXSR Exit Self Refresh and Active Command
(6)
55 70 70 ns
tRFC Auto Refresh Period 60 60 70 ns
tREF Refresh Cycle Time (4096) 64 64 64 ms
Notes:
1. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device
operation is ensured. (V
DD and VDDQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The
two AUTO REFRESH command wake-ups should be repeated anytime the tREF refresh requirement is exceeded.
2. Measured with t
T = 0.5 ns.
3. The reference level is 1.5V when measuring input signal timing. Rise/fall times are measured between V
IH (min.) and VIL
(max.).
4. Access time is measured at 1.5V with the load shown in the figure below.
5. The time t
HZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)
when the output is in the high impedance state.
6. CLK must be toggled a minimum of two times during this period.

IS42S32200E-6BI-TR

Mfr. #:
Manufacturer:
Description:
DRAM 64M (2Mx32) 166MHz SDRAM, 3.3v
Lifecycle:
New from this manufacturer.
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